Low power memory cell with high sensing margin

Patent metadata

Field	Value
Publication number	US-9583167-B2
Application number	US-201514698882-A
Country	US
Kind code	B2
Filing date	Apr 29, 2015
Priority date	Apr 29, 2015
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

Memory cell, method for operating the memory cell and method of forming the memory cell are disclosed. The memory cell includes a first selector having a first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, and a second selector having at least a second select transistor with a second gate coupled to a second wordline and first and second S/D regions. The memory cell includes a first magnetic tunnel junction (MTJ) element coupled between a first bit line and the first S/D region of the first select transistor, and a second MTJ element coupled between a second bit line and the first S/D region of the second select transistor.

First claim

The invention claimed is:

1. A memory cell comprising:
a first magnetic tunnel junction (MTJ) element coupled to a first bit line;
a second MTJ element coupled to a second bit line, wherein the first and second MTJ elements have a common node;
a first selector having a first selector first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, wherein the common node of the first and second MTJ elements is coupled to the first S/D region of the first selector first select transistor; and
a second selector having a second selector first select transistor with a second gate coupled to a second wordline and first and second S/D regions, and a second selector second select transistor with a third gate coupled to the second wordline and first and second S/D regions, wherein the first S/D regions of the second selector first select transistor and second selector second select transistor are a common first S/D region coupled to the second bitline.

2. The memory cell of claim 1 wherein the first word line is a read wordline and the second wordline is a write wordline.

3. The memory cell of claim 2 wherein the second S/D regions of the first selector first select transistor and second selector first select transistor are a common second S/D region and the common second S/D region is coupled to ground.

4. The memory cell of claim 2 wherein the second selector first select transistor and second selector second select transistor are coupled in parallel.

5. The memory cell of claim 1 wherein each of the first and second MTJ elements comprises:
a top electrode;
a bottom electrode;
a MTJ stack in between the top and bottom electrodes, wherein the MTJ stack comprises a magnetically free layer, a magnetically fixed layer and a tunneling barrier layer between the free and fixed layers.

6. The memory cell of claim 5 wherein the bottom electrodes of the first and second MTJ elements are a common bottom electrode.

7. A method of operating a memory cell comprising:
providing a memory cell comprising
a first magnetic tunnel junction (MTJ) element coupled to a first bit line;
a second MTJ element coupled to a second bit line, wherein the first and second MTJ elements have a common node;
a first selector having a first selector first select transistor with a first gate terminal coupled to a first wordline and first and second S/D terminals, wherein the common node of the first and second MTJ elements is coupled to the first S/D terminal of the first selector first select transistor,
a second selector having
a second select transistor with a second gate terminal coupled to a second wordline and first and second S/D terminals,
a third select transistor with a third gate terminal coupled to the second wordline and first and second S/D terminals, wherein the first S/D terminals of the second and third select transistors are a common first S/D terminal; and

performing a read operation or write operation with the memory cell.

8. The method of claim 7 wherein:
the first wordline is a read wordline and the second wordline is a write wordline; and
the second S/D terminals of the first and second select transistors are coupled to a common source line.

9. The method of claim 8 wherein performing a read operation comprises:
providing an active read signal to the read wordline and providing an inactive signal to the write wordline; and
forming a read path from the first and second bitlines to ground.

10. A method of operating a memory cell comprising:
providing a memory cell comprising
a first selector having a first select transistor with a first gate terminal coupled to a read wordline and first and second S/D terminals,
a second selector having
a second select transistor with a second gate terminal coupled to a write wordline and first and second S/D terminals,
a third select transistor with a third gate terminal coupled to the write wordline and first and second S/D terminals, wherein the first S/D terminals of the second and third select transistors are a common first S/D terminal,

wherein the second S/D terminals of the first and second select transistors are coupled to a common source line,
a first magnetic tunnel junction (MTJ) element coupled between a first bit line and the first S/D terminal of the first select transistor, and
a second MTJ element coupled to a second bit line and the first S/D terminals of the second and third select transistors; and

performing a read operation or write operation with the memory cell, wherein performing a write operation comprises:
providing an active write signal to the write wordline and providing an inactive signal to the read wordline; and
forming a write path from the first bitline to source line by floating the second bitline.

11. The method of claim 10 wherein, during the write operation, the first and second MTJ elements are in two opposite states such that one of the first and second MTJ elements is in a parallel state and the other of the first and second MTJ elements is in an anti-parallel state.

12. A method for forming a memory cell comprising:
providing a cell selector unit on a substrate comprising
forming a first selector having a first selector first select transistor with a first gate and first and second S/D regions,
forming a second selector which comprises forming a second selector first select transistor with a second gate and first and second S/D regions, and a second selector second select transistor with a third gate and first and second S/D regions;

providing a cell dielectric layer on the substrate;
forming a storage unit in the cell dielectric layer which comprises forming first and second magnetic tunnel junction (MTJ) elements;
forming an upper metal level over the cell dielectric layer which comprises forming first and second bitlines in the upper metal level;
coupling the first gate of the first selector first select transistor to a first wordline;
coupling the second and third gates of the second selector first select transistor and second selector second select transistor to a second wordline;
coupling the first MTJ element between the first bit line and the first S/D region of the first selector first select transistor; and
coupling the second MTJ element to the second bit line and the first S/D region of the second selector first select transistor.

13. The method of claim 12 wherein the first S/D regions of the second selector first select transistor and second selector second select transistor are common first S/D regions coupled to the second bit line.

14. The method of claim 13 wherein the second S/D regions of the first selector first select transistor and second selector first select transistor are a common second S/D region.

15. The method of claim 14 wherein the first wordline is a read wordline and the second wordline is a write wordline.

16. The method of claim 14 comprising coupling the common second S/D region to ground.

17. The method of claim 13 wherein the second selector first select transistor and second selector second select transistor are coupled in parallel.

18. The method of claim 12 wherein forming the first and second MTJ elements comprises:
forming a top electrode layer and a bottom electrode layer in the cell dielectric layer;
forming MTJ stack layers in between the top and bottom electrodes, wherein the MTJ stack comprises a magnetically free layer, a magnetically fixed layer and a tunneling barrier layer between the free and fixed layers.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Chan Tze Ho Simon
• Hong Yang
• Poh Yong Wee Francis

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/1657

  Word-line or row circuits · CPC title

• G11C11/1659

  Cell access · CPC title