Test bench transaction synchronization in a debugging environment

Patent metadata

Field	Value
Publication number	US-9582625-B2
Application number	US-201313924156-A
Country	US
Kind code	B2
Filing date	Jun 21, 2013
Priority date	Jun 22, 2012
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

This application discloses a design verification tool to simulate a circuit design with a test bench to generate a simulated output for the circuit design and a simulation log corresponding to operation of the test bench during the simulation of the circuit design. The design verification tool can determine whether the simulated output for the circuit design is different than an expected output for the circuit design. A debug tool can synchronize the simulated output for the circuit design with test bench transactions from the simulation log that prompted the generation of the simulated output for the circuit design when the simulated output of the circuit design is different than the expected output of the circuit design.

First claim

The invention claimed is:

1. A method comprising:
simulating, by a computing system, a circuit design with a test bench to generate a simulated output for the circuit design and to generate a simulation log storing messages corresponding to operation of the test bench during the simulation of the circuit design;
parsing, by the computing system, the simulation log to identify which of the messages in the simulation log correspond to test bench transactions based, at least in part, on types of the messages in the simulation log and formats for the test bench transactions; and
synchronizing, by the computing system, the simulated output for the circuit design with the test bench transactions identified from the simulation log that prompted the generation of the simulated output for the circuit design.

2. The method of claim 1 , wherein parsing the simulation log extracts the test bench transactions from the simulation log prior to the synchronization.

3. The method of claim 1 , further comprising prompting, by the computing system, display of the test bench transactions and the simulated output for the circuit design in temporal synchronization with each other.

4. The method of claim 3 , wherein the simulated output for the circuit design and the test bench transactions are displayed in a common window.

5. The method of claim 1 , further comprising receiving, by the computing system, a selection corresponding to a time during the simulation of the circuit design, wherein prompting display of the test bench transactions and the simulated output for the circuit design is performed in response to the selection.

6. The method of claim 1 , further comprising:
synchronizing, by the computing system, a source code for the test bench with the test bench transactions from the simulation log; and
prompting, by the computing system, display of the source code for the test bench and the test bench transactions in temporal synchronization with each other.

7. The method of claim 6 , wherein the source code for the test bench and the test bench transactions are displayed in a common window.

8. The method of claim 6 , further comprising receiving, by the computing system, a selection corresponding to a time during the simulation of the circuit design, wherein prompting display of the source code for the test bench and the test bench transactions is performed in response to the selection.

9. The method of claim 1 , wherein the simulated output for the circuit design includes waveform data.

10. A system comprising:
a circuit design simulation tool configured to simulate a circuit design with a test bench, generate a simulated output for the circuit design, and generate a simulation log storing messages corresponding to operation of the test bench during the simulation of the circuit design; and
a debug tool configured to parse the simulation log to identify which of the messages in the simulation log correspond to test bench transactions based, at least in part, on types of the messages in the simulation log and formats for the test bench transactions, wherein the debug tool is configured to synchronize the simulated output for the circuit design with the test bench transactions identified from the simulation log that prompted the generation of the simulated output for the circuit design.

11. The system of claim 10 , wherein the debug tool is configured to parse the simulation log to extract the test bench transactions from the simulation log prior to the synchronization.

12. The system of claim 10 , wherein the debug tool is configured to prompt display of the test bench transactions and the simulated output for the circuit design in temporal synchronization with each other.

13. The system of claim 12 , wherein the simulated output for the circuit design and the test bench transactions are displayed in a common window.

14. The system of claim 12 , wherein the debug tool is configured to identify a selection corresponding to a time during the simulation of the circuit design, and prompt display of the test bench transactions and the simulated output for the circuit design in response to the selection.

15. The system of claim 10 , wherein the debug tool is configured to synchronize a source code for the test bench with the test bench transactions from the simulation log, and prompt display of the source code for the test bench and the test bench transactions in temporal synchronization with each other.

16. The system of claim 15 , wherein the source code for the test bench and the test bench transactions are displayed in a common window.

17. The system of claim 15 , wherein the debug tool is configured to identify a selection corresponding to a time during the simulation of the circuit design, and prompt display of the source code for the test bench and the test bench transactions in response to the selection.

18. The system of claim 10 , wherein the simulated output for the circuit design includes waveform data.

19. A method comprising:
parsing, by a computing system, a simulation log having messages corresponding to operation of a test bench during a simulation of a circuit design based, at least in part, on types of the messages in the simulation log and formats for test bench transactions;
extracting, by the computing system, the test bench transactions from the simulation log based on the parsing; and
synchronizing, by the computing system, the test bench transactions from the simulation log with waveform data generated during the simulation of the circuit design; and
prompting, by the computing system, display of the test bench transactions and the simulated output for the circuit design in temporal synchronization with each other.

20. The method of claim 19 , wherein the simulated output for the circuit design and the test bench transactions are displayed in a common window.

21. The method of claim 19 , further comprising:
synchronizing, by the computing system, a source code for the test bench with the test bench transactions from the simulation log; and
prompting, by the computing system, display of the source code for the test bench and the test bench transactions in temporal synchronization with each other.

22. The method of claim 21 , wherein the source code for the test bench and the test bench transactions are displayed in a common window.

23. The method of claim 21 , further comprising receiving, by the computing system, a selection corresponding to a time during the simulation of the circuit design, wherein prompting display of the source code for the test bench and the test bench transactions is performed in response to the selection.

24. The method of claim 19 , further comprising receiving, by the computing system, a selection corresponding to a time during the simulation of the circuit design, wherein prompting display of the test bench transactions and the waveform data for the circuit design is performed in response to the selection.

25. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
parsing a simulation log having messages corresponding to operation of a test bench during a simulation of a circuit design based, at least in part, on types of the messages in the simulation log and formats for test bench transactions;
extracting the test bench transactions from the simulation log based

Assignees

• Agarwala Badruddin
• Parikh Tarak
• Bhat Vivek
• Joshi Neeraj
• Mentor Graphics Corp

Inventors

• Agarwala Badruddin
• Parikh Tarak
• Bhat Vivek
• Joshi Neeraj

Classifications

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F17/5045 Primary

  Physics · mapped topic

• G06F17/5022

  Physics · mapped topic

• G06F30/3308 Primary

  using simulation · CPC title

• G06F30/30

  Circuit design · CPC title