Systems, apparatuses, and methods for performing a double blocked sum of absolute differences

Patent metadata

Field	Value
Publication number	US-9582464-B2
Application number	US-201113992229-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 23, 2011
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.

First claim

What is claimed is:

1. A method comprising:
decoding a single instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode;
executing the decoded single instruction to, on a per data lane basis, compute a sum of absolute differences (SAD) of selected quadruplets of data elements of the first and second sources, wherein the quadruplets are selected using consecutive pairs of bits of the immediate; and
storing each calculated SAD into the destination vector register, wherein the stored SADs comprise:
in a least significant position of the destination register, the stored SAD is an absolute value of a least significant data element position of the first source minus a least significant data element position of the second source that is added to an absolute value of a second-most least significant data element position of the first source minus a second-most least significant data element position of the second source that is added to an absolute value of a third-most least significant data element position of the first source minus a third-most least significant data element position of the second source that is added to an absolute value of a fourth-most least significant data element position of the first source minus a fourth-most least significant data element position of the second source,
in a second-most least significant position of the destination register, the stored SAD is an absolute value of a least significant data element position of the first source minus a second-most least significant data element position of the second source that is added to an absolute value of a second-most least significant data element position of the first source minus a third-most least significant data element position of the second source that is added to an absolute value of a third-most least significant data element position of the first source minus a fourth-most least significant data element position of the second source that is added to an absolute value of a fourth-most least significant data element position of the first source minus a fifth-most least significant data element position of the second source,
in a third-most least significant position of the destination register, the stored SAD is an absolute value of a fifth-most least significant data element position of the first source minus a third-most least significant data element position of the second source that is added to an absolute value of a sixth-most least significant data element position of the first source minus a fourth-most least significant data element position of the second source that is added to an absolute value of a seventh-most least significant data element position of the first source minus a fifth-most least significant data element position of the second source that is added to an absolute value of a eighth-most least significant data element position of the first source minus a sixth-most least significant data element position of the second source, and
in a fourth-most least significant position of the destination register, the stored SAD is an absolute value of a fifth-most least significant data element position of the first source minus a fourth-most least significant data element position of the second source that is added to an absolute value of a sixth-most least significant data element position of the first source minus a fifth-most least significant data element position of the second source that is added to an absolute value of a seventh-most least significant data element position of the first source minus a sixth-most least significant data element position of the second source that is added to an absolute value of a eighth-most least significant data element position of the first source minus a seventh-most least significant data element position of the second source.

2. The method of claim 1 , wherein the data elements of the selected quadruplets of the first and second sources are byte sized.

3. The method of claim 2 , wherein the data elements of the destination register are word sized.

4. The method of claim 1 , wherein the first source operand is a vector register and the second source operand is a memory location.

5. The method of claim 1 , wherein the first and second source operands are vector registers.

6. The method of claim 1 , wherein the first and second source operands and the destination vector register operand are all of the same size selected from the group consisting of 128-bit, 256-bit, and 512-bit.

7. An article of manufacture comprising:
a non-transitory machine-readable storage medium having stored thereon an occurrence of an instruction, wherein the instruction's format specifies as its source operands a first and second source and an immediate and specifies as its destination a single destination vector register, and wherein the instruction format includes an opcode which instructs a machine, responsive to the single occurrence of the single instruction, to cause on a per data lane basis, a computation of a SAD of selected quadruplets of data elements of the first and second sources and storage of each calculated SAD into the destination vector register, wherein the quadruplets are selected using consecutive pairs of bits of the immediate, wherein the stored SADs comprise:
in a least significant position of the destination register, the stored SAD is an absolute value of a least significant data element position of the first source minus a least significant data element position of the second source that is added to an absolute value of a second-most least significant data element position of the first source minus a second-most least significant data element position of the second source that is added to an absolute value of a third-most least significant data element position of the first source minus a third-most least significant data element position of the second source that is added to an absolute value of a fourth-most least significant data element position of the first source minus a fourth-most least significant data element position of the second source,
in a second-most least significant position of the destination register, the stored SAD is an absolute value of a least significant data element position of the first source minus a second-most least significant data element position of the second source that is added to an absolute value of a second-most least significant data element position of the first source minus a third-most least significant data element position of the second source that is added to an absolute value of a third-most least significant data element position of the first source minus a fourth-most least significant data element position of the second source that is added to an absolute value of a fourth-most least significant data element position of the first source minus a fifth-most least significant data element position of the second source,
in a third-most least significant position of the destination register, the stored SAD is an absolute value of a fifth-most least significant data element position of the first source minus a third-most least significant data element position of the second source that is added to an absolute value of a sixth-most least significant data element position of the first source minus a fourth-most least significant data element position of the second source that is added to an absolute value of a seventh-most least significant data element position of the first source minus a fifth-most least significant data element position of the second source that is added to an absolute value of a eighth-most least significant data element position of the first source minus a sixth-most least significant data element position of the second sourc

Assignees

• Ould-Ahmed-Vall Elmoustapha
• Hagog Mostafa
• Valentine Robert
• Gradstein Amit
• Rubanovich Simon
• Sperber Zeev
• Intel Corp

Inventors

• Ould-Ahmed-Vall Elmoustapha
• Hagog Mostafa
• Valentine Robert
• Gradstein Amit
• Rubanovich Simon
• Sperber Zeev

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F7/50

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title

• G06F15/78 Primary

  comprising a single central processing unit · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title