Method and device to distribute code and data stores between volatile memory and non-volatile memory

Patent metadata

Field	Value
Publication number	US-9582216-B2
Application number	US-201113977295-A
Country	US
Kind code	B2
Filing date	Dec 28, 2011
Priority date	Dec 28, 2011
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A method, device, and system to distribute code and data stores between volatile and non-volatile memory are described. In one embodiment, the method includes storing one or more static code segments of a software application in a phase change memory with switch (PCMS) device, storing one or more static data segments of the software application in the PCMS device, and storing one or more volatile data segments of the software application in a volatile memory device. The method then allocates an address mapping table with at least a first address pointer to point to each of the one or more static code segments, at least a second address pointer to point to each of the one or more static data segments, and at least a third address pointer to point to each of the one or more volatile data segments.

First claim

We claim:

1. A method comprising:
reading a volatile bit variable for data segments of a software application, wherein a cleared volatile bit is to indicate a static data segment unlikely to be changed during execution of the software application, and a set volatile bit is to indicate a volatile data segment likely to be changed during execution of the software application;
storing one or more static code segments of the software application in a phase nonvolatile random access memory (NVRAM) device, wherein the NVRAM device is to store the static code segments as byte addressable elements capable to be randomly accessed;
storing one or more static data segments of the software application in the NVRAM device, based on reading the volatile bit variable to indicate the static data segments, wherein the NVRAM device is to store the static data segments as byte addressable elements capable to be randomly accessed;
storing one or more volatile data segments of the software application in a volatile memory device, based on reading the volatile bit variable to indicate the volatile data segments;
allocating an address mapping table with at least a first address pointer to point to the one or more static code segments, at least a second address pointer to point to the one or more static data segments, and at least a third address pointer to point to the one or more volatile data segments.

2. The method of claim 1 , wherein the storing of the static code segments, the static data segments, and the volatile data segments further comprises:
loading the software application for execution;
identifying for the software application static code segments, static data segments, and volatile data segments; and
storing the static code segments, the static data segments, and the volatile data segments in accordance with the identifying.

3. The method of claim 1 , further comprising:
initially storing all data segments of the software application in the NVRAM device;
for a given data segment within the data segments, transferring the given data segment to the volatile memory device in response to reception of a rewrite request for the given data segment during execution of the software application.

4. The method of claim 1 , further comprising:
executing static code segments and static data segments directly from the NVRAM device without transferring to the volatile memory device.

5. The method of claim 1 , wherein the software application comprises firmware and the volatile memory device comprises a static random access memory (SRAM) device integrated into an embedded controller.

6. The method of claim 1 , wherein the NVRAM device comprises a memory device coupled directly to a memory controller on a memory bus.

7. A device comprising:
an embedded controller to
execute one or more static code segments of a firmware directly from a nonvolatile random access memory (NVRAM) device, wherein the NVRAM device is to store the static code segments as byte addressable elements capable to be randomly accessed;
execute one or more static data segments of the firmware directly from the NVRAM device, the static data segments stored in the NVRAM device based on a cleared volatile bit to indicate a static data segment unlikely to be changed during execution of the software application, wherein the NVRAM device is to store the static data segments as byte addressable elements capable to be randomly accessed; and
execute one or more volatile data segments of the firmware from a static random access memory device integrated into the embedded controller, the volatile data segments stored in the static random access memory device based on a set volatile bit is to indicate a volatile data segment likely to be changed during execution of the software application.

8. The device of claim 7 , further comprising:
a cryptographic verification module to authenticate a new firmware code or data segment received from an external source;
wherein the embedded controller is configured to require authentication before execution of the new firmware code or data segment.

9. The device of claim 7 , wherein the NVRAM device comprises a memory device coupled directly to a memory controller on a memory bus coupled to the embedded controller.

10. A system comprising:
a processor;
a volatile memory device to store memory allocation logic; and
a nonvolatile random access memory NVRAM device;
wherein the memory allocation logic configured to cause the processor to
read a volatile bit variable for data segments of a software application, wherein a cleared volatile bit is to indicate a static data segment unlikely to be changed during execution of the software application, and a set volatile bit is to indicate a volatile data segment likely to be changed during execution of the software application;
store one or more static code segments of a software application and one or more static data segments of the software application in the NVRAM device, wherein the NVRAM device is to store the static code segments as byte addressable elements capable to be randomly accessed;
store one or more static data segments of the software application in the NVRAM device, based on a read of the volatile bit variable to indicate the static data segments, wherein the NVRAM device is to store the static data segments as byte addressable elements capable to be randomly accessed;
store one or more volatile data segments of the software application in the volatile memory device, based on a read of the volatile bit variable to indicate the volatile data segments; and
allocate an address mapping table in the volatile memory with at least a first address pointer to point to the one or more static code segments, at least a second address pointer to point to the one or more static data segments, and at least a third address pointer to point to the one or more volatile data segments.

11. The system of claim 10 , further comprising the processor to load the software application for execution, identify for the software application static code segments, static data segments, and volatile data segments, and store the static code segments, the static data segments, and the volatile data segments in accordance with the identifying.

12. The system of claim 10 , wherein the processor is to:
initially store all data segments of the software application in the NVRAM device; and
for a given data segment within the data segments, transfer the given data segment to the volatile memory device in response to reception of a rewrite request for the given data segment during execution of the software application.

13. The system of claim 10 , wherein the processor is to:
execute static code segments and static data segments directly from the NVRAM device without transferring to the volatile memory device.

14. The system of claim 10 , wherein the processor comprises an embedded controller, the software application comprises firmware, and the volatile memory device comprises a static random access memory (SRAM) device integrated into an embedded controller.

15. The system of claim 10 , wherein the NVRAM device comprises a memory device coupled directly to a memory controller on a memory bus coupled to the processor.

Assignees

• Vembu Balaji
• Ramadoss Murali
• Intel Corp

Inventors

• Vembu Balaji
• Ramadoss Murali

Classifications

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F3/0638 Primary

  Organizing or formatting or addressing of data · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title