Self aligned patterning with multiple resist layers

Patent metadata

Field	Value
Publication number	US-9581900-B2
Application number	US-201514753523-A
Country	US
Kind code	B2
Filing date	Jun 29, 2015
Priority date	Feb 1, 2013
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A method for using self aligned multiple patterning with multiple resist layers includes forming a first patterned resist layer onto a substrate, forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer, and forming a second patterned resist layer over the spacer layer and depositing a masking layer. The method further includes performing a planarizing process to expose the first patterned resist layer, removing the first resist layer, removing the second resist layer, and exposing the substrate.

First claim

What is claimed is:

1. A method comprising:
forming a first patterned resist layer over a substrate;
forming a spacer layer over the first patterned resist layer such that the spacer layer covers the first patterned resist layer;
forming a second patterned resist layer over the spacer layer;
forming a hard mask layer over the second patterned resist layer; and
removing a first portion of the second patterned resist layer and a portion of the spacer layer to expose the first patterned resist layer, wherein a second portion of the second patterned resist layer is disposed over the substrate after removing the first portion of the second patterned resist layer.

2. The method of claim 1 , wherein forming the spacer layer over the first patterned resist layer such that the spacer layer covers the first patterned resist layer includes forming the spacer layer directly on the first patterned resist layer.

3. The method of claim 1 , wherein removing the first portion of the second patterned resist layer and a portions of the spacer layer to expose the first patterned resist layer further includes removing a portion of the hard mask layer to form a patterned hard mask layer.

4. The method of claim 3 , further comprising etching the spacer layer to form a patterned spacer layer by using the patterned hardmask as a mask.

5. The method of claim 4 , further comprising etching the substrate while using the patterned hardmask and the patterned spacer layer as a mask.

6. The method of claim 1 , wherein forming the second patterned resist layer over the spacer layer includes forming the second patterned resist layer over the first patterned resist layer such that portion of the second patterned resist layer overlaps a portion of the first patterned resist layer.

7. The method of claim 1 , wherein removing the first portion of the second patterned resist layer and a portion of the spacer layer to expose the first patterned resist layer includes performing a chemical mechanical polishing process.

8. A method comprising:
forming a first patterned resist layer over a substrate;
forming a spacer layer covering the first patterned resist;
forming a masking layer over the spacer layer;
forming a second patterned resist layer over the masking layer;
etching the masking layer while using the second patterned resist layer as a mask;
removing a portion of the spacer layer to expose the first patterned resist layer;
removing the first patterned resist layer; and
etching the substrate while using the masking layer and the spacer layer as a mask.

9. The method of claim 8 , further comprising removing the second patterned resist layer prior removing the portion of the spacer layer to expose the first patterned resist layer.

10. The method of claim 8 , wherein forming the spacer layer covering the first patterned resist includes forming the spacer layer such that it defines a recess, and
wherein forming the masking layer includes forming the masking layer within the recess.

11. The method of claim 10 , wherein the masking layer is recessed within the recess such that a top portion of the recess is unfilled by the masking layer after forming the masking layer over the spacer layer.

12. The method of claim 11 , wherein forming the second patterned resist layer over the masking layer includes forming the second patterned resist layer within the portion of the recess.

13. The method of claim 10 , wherein the masking layer is disposed within the recess when etching the substrate while using the masking layer and the spacer layer as the mask.

14. The method of claim 8 , wherein removing the portion of the spacer layer to expose the first patterned resist layer further includes removing another portion of the spacer layer to expose the substrate.

15. A method comprising:
forming a first resist layer over a substrate;
forming a dielectric layer over the first resist layer such that dielectric layer covers the first resist layer;
forming a second resist layer over the dielectric layer;
removing a portion of the dielectric layer to expose the first resist layer; and
removing the first resist layer; and
etching the substrate while using the dielectric layer as a mask.

16. The method of claim 15 , wherein the first resist layer and the second resist layer are formed using a different type of mask tone.

17. The method of claim 15 , wherein removing the removing the first resist layer includes removing the second resist layer after removing the portion of the dielectric layer to expose the first resist layer.

18. The method of claim 15 , further comprising forming a masking layer over the second resist layer.

19. The method of claim 15 , wherein after removing the first resist layer the substrate is free of the first resist layer.

20. The method of claim 15 , wherein removing the portion of the dielectric layer to expose the first resist layer includes removing a first portion of the second resist layer to expose the first resist layer, and
wherein a second portion of the second resist layer is disposed over the substrate after removing the first portion of the second resist layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shieh Ming-Feng
• Lai Chih-Ming
• Hsieh Ken-Hsien
• Liu Ru-Gun
• Chang Shih-Ming

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• G03F7/0035 Primary

  Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface · CPC title

• G03F7/20

  Exposure; Apparatus therefor (photographic printing apparatus for making copies G03B27/00) · CPC title

• G03F7/40

  Treatment after imagewise removal, e.g. baking · CPC title

• H01L21/0337

  Electricity · mapped topic