Fractional phase locked loop (PLL) architecture

Patent metadata

Field	Value
Publication number	US-9577646-B1
Application number	US-201514820894-A
Country	US
Kind code	B1
Filing date	Aug 7, 2015
Priority date	Aug 7, 2015
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

First claim

What is claimed is:

1. A frequency divider, comprising:
a plurality of cascaded divider stages forming a divider chain, wherein each of the divider stages is configured to receive one or more respective control bits and to set a divider value of the divider stage based on the one or more respective control bits, and wherein the plurality of cascaded divider stages is configured to propagate an input signal down the divider chain from a first one of the divider stages to a last one of the divider stages, to divide a frequency of the input signal, and to propagate a modulus signal up the divider chain from the last one of the divider stages to the first one of the divider stages, and each of the divider stages is configured to output a respective local load signal when the modulus signal propagates out of the divider stage; and
an extension device coupled to the plurality of divider stages, wherein, for each of the divider stages, the extension device is configured to receive the respective local load signal from the divider stage and to input the one or more respective control bits for the divider stage to the divider stage based on the respective local load signal.

2. The frequency divider of claim 1 , wherein, for each of the divider stages, the extension device is configured to input the one or more respective control bits for the divider stage to the divider stage on an edge of the respective local load signal.

3. The frequency divider of claim 2 , wherein the edge of the respective local load signal is a rising edge of the respective local load signal.

4. The frequency divider of claim 1 , wherein the extension device comprises a plurality of load devices, each of the load devices corresponds to a respective one of the divider stages, and each of the load devices comprises:
a logic circuit configured to generate the one or more respective control bits for the respective divider stage; and
a flip-flop configured to receive the one or more respective control bits from the respective logic circuit, to receive the respective local load signal from the respective divider stage, and to output the one or more respective control bits to the respective divider stage on an edge of the respective local load signal.

5. The frequency divider of claim 4 , wherein the edge of the respective local load signal is a rising edge of the respective local load signal.

6. The frequency divider of claim 1 , wherein the extension device is configured to receive a plurality of control bits from a delta-sigma modulator and to convert the plurality of control bits into the respective control bits for the divider stages.

7. The frequency divider of claim 1 , wherein at least one of the divider stages is a 1/2/3 divider stage, and the respective one or more control bits comprises a respective program bit and a respective divide bit.

8. The frequency divider of claim 7 , wherein the 1/2/3 divider stage is configured to set the respective divider value to one if the respective divide bit has a first logic state, and to set the respective divider value to two or three depending at least in part on a logic state of the respective program bit if the divide bit has a second logic state.

9. The frequency divider of claim 1 , further comprising an output latch configured to receive the modulus signal from a modulus output of one of the divider stages, to receive the input signal, and to retime the received modulus signal with the received input signal to generate an output signal of the frequency divider.

10. The frequency divider of claim 9 , wherein the output latch is configured to align an edge of the received modulus signal with an edge of the received input signal.

11. A frequency divider, comprising:
a plurality of cascaded divider stages forming a divider chain, wherein the plurality of cascaded divider stages is configured to receive a plurality of control bits that set a divisor of the plurality of cascaded divider stages, to propagate an input signal down the divider chain from a first one of the divider stages, to a last one of the divider stages, to divide a frequency of the input signal by the divisor, and to propagate a modulus signal up the divider chain from the last one of the divider stages to the first one of the divider stages; and
an output latch configured to receive the modulus signal from a modulus output of one of the divider stages, to receive the input signal, and to retime the received modulus signal with the received input signal to generate an output signal of the frequency divider.

12. The frequency divider of claim 11 , wherein the output latch is configured to align an edge of the received modulus signal with an edge of the received input signal.

13. The frequency divider of claim 12 , wherein the received modulus signal comprises a single pulse during a divider period, the divider period being approximately equal to a period of the input signal multiplied by the divisor of the plurality of cascaded divider stages.

14. The frequency divider of claim 11 , wherein each of the divider stages is configured to retime the modulus signal at the divider stage with an edge of the input signal received at a respective frequency input of the divider stage.

15. A method for frequency division, comprising:
propagating an input signal down a chain of cascaded divider stages from a first one of the divider stages to a last one of the divider stages, wherein the chain of cascaded divider stages divides a frequency of the input signal;
propagating a modulus signal up the chain of cascaded divider stages from the last one of the divider stages to the first one of the divider stages;
for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage; and
for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

16. The method of claim 15 , wherein, inputting the one or more respective control bits for each of the divider stages comprises inputting the one or more respective control bits on an edge of the respective local load signal.

17. The method of claim 16 , wherein the edge of the respective local load signal is a rising edge of the respective local load signal.

18. The method of claim 15 , further comprising:
receiving the modulus signal from a modulus output of one of the divider stages;
receiving the input signal; and
retiming the received modulus signal with the received input signal to generate an output signal.

19. The method of claim 18 , retiming the received modulus signal comprises aligning an edge of the received modulus signal with an edge of the received input signal.

20. An apparatus for frequency division, comprising:
means for propagating an input signal down a chain of cascaded divider stages from a first one of the divider stages to a last one of the divider stages, wherein the chain of cascaded divider stages divides a frequency of the input signal;
means for propagating a modulus signal up the chain of cascaded divider stages from the last one of the divider stages to the first one of the divider stages;
for each of the divider stages, means for generating a respective local load signal when the modulus signal propagates out of the divider stage; and
for each of the divider stages, means for inputting one or more respective control bits to the divider stage based on the

Assignees

• Qualcomm Inc

Inventors

• Pandita Bupesh
• Cohen Hanan
• Hailu Eskinder
• Arcudia Kenneth Luis

Classifications

• H03L7/1974

  for fractional frequency division · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03K21/10 Primary

  comprising logic circuits · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/197

  a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)} · CPC title