Phase interpolator

Patent metadata

Field	Value
Publication number	US-9577622-B2
Application number	US-201514706874-A
Country	US
Kind code	B2
Filing date	May 7, 2015
Priority date	May 7, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

Phase interpolators are provided where an adjustment current is added to currents from a plurality of switchable current sources, for example to reduce an integrated nonlinearity.

First claim

The invention claimed is:

1. A phase interpolator device, comprising:
a plurality of current sources,
a plurality of current selection switches associated with the plurality of current sources to selectively couple the current sources to at least two summing nodes,
a phase signal input stage to receive at least two input signals having different phases, the phase input stage to modify a first current from a first summing node of the at least two summing nodes based on a first input signal of the at least two input signals to generate a first modified current and to modify a second current from a second summing node of the at least two summing nodes based on a second input signal of the at least two input signals to generate a second modified current,
an output stage to generate an output signal based on the first modified current and the second modified current, and
a current adjustment circuit to adjust a current through at least one of the first summing node or the second summing node.

2. The device of claim 1 , wherein an output of the current adjustment circuit is coupled with an output of the plurality of current selection switches at the at least one summing node.

3. The device of claim 1 , wherein the current adjustment circuit is to adjust a current output by the plurality of current sources.

4. The device of claim 1 , wherein the current sources of the plurality of current sources are to generate nominally equal currents.

5. The device of claim 1 , wherein the adjustment circuit is to adjust a current at the at least one summing node based on a switching state of the plurality of current selection switches.

6. The device of claim 5 , further comprising a memory for storing a look-up table, the look-up table storing information describing a dependency between the current adjustment by the current adjustment circuit and the switching state.

7. The device of claim 1 , wherein the plurality of current selection switches is controllable by a digital control word.

8. The device of claim 1 , wherein the adjustment circuitry comprises a plurality of further current sources, the plurality of further current sources being selectively coupled to the at least one summing node.

9. The device of claim 8 , wherein at least one of the plurality of further current sources is to produce a smaller current than each of the plurality of current sources.

10. The device of claim 8 , wherein the plurality of further current sources are matched with the plurality of current sources.

11. The device of claim 8 , wherein the plurality of further current sources are controllable by a digital control word.

12. The device of claim 8 , wherein the plurality of further current sources are to generate different currents.

13. The device of claim 1 , wherein the input stage comprises a plurality of transistor pairs.

14. The device of claim 13 , further comprising a plurality of switches to selectively enable a part of the differential pairs.

15. The device of claim 1 , wherein the current adjustment circuitry is to generate the adjustment current to reduce an integrated nonlinearity of a phase interpolation.

16. A method comprising:
calibrating a phase interpolator device by:
determining a first phase that is output by the phase interpolator device, wherein the first phase is associated with a control signal defined by a first value;
increasing the control signal to a second value;
determining a phase that is output by the phase interpolator device, wherein the second phase is associated with the control signal defined by the second value;
determining a phase change between the first phase and the second phase that is caused by the increasing of the control signal;
outputting, to the phase interpolation device, the control signal defined by the second value and a candidate correction signal defined by a third value;
determining a third phase that is output by the phase interpolator device, wherein the third phase is associated with the control signal defined by the second value and the candidate correction signal defined by the third value;
outputting, to the phase interpolation device, the control signal defined by the second value and a candidate correction signal defined by a fourth value;
determining a fourth phase that is output by the phase interpolator device, wherein the fourth phase is associated with the control signal defined by the second value and the candidate correction signal defined by the fourth value; and
determining, from the candidate correction signal defined by the third value and the candidate correction signal defined by the fourth value, a correction signal associated with the control signal defined by the second value, wherein the correction signal is used to reduce a difference between the phase change and a target value of the phase change.

17. The method of claim 16 , wherein the correction signal is a first correction signal and the phase change is a first phase change, the method further comprising:
increasing the control signal from the second value to a fifth value;
determining a fifth phase that is output by the phase interpolator device, wherein the fifth phase is associated with the control signal defined by the fifth value;
determining a second phase change between the second phase and the fifth phase;
outputting, to the phase interpolation device, the control signal defined by the fifth value and a candidate correction signal defined by a sixth value;
determining a sixth phase that is output by the phase interpolator device, wherein the sixth phase is associated with the control signal defined by the fifth value and the candidate correction signal defined by the sixth value;
outputting, to the phase interpolation device, the control signal defined by the fifth value and a candidate correction signal defined by a seventh value;
determining a seventh phase that is output by the phase interpolator device, wherein the seventh phase is associated with the control signal defined by the fifth value and the candidate correction signal defined by the seventh value; and
determining, from the candidate correction signal defined by the sixth value and the candidate correction signal defined by the seventh value, a second correction signal associated with the control signal defined by the fifth value.

18. The method of claim 16 , further comprising storing the control signal together with the determined correction signal associated with the control signal.

19. The method of claim 16 , wherein the control signal is a digital word, and increasing the control signal comprises increasing the digital word by one least significant bit.

20. The method of claim 16 , wherein determining the correction signal comprises:
selecting, as the correction signal, from the candidate correction signal defined by the third value and the candidate correction signal defined by the fourth value, a candidate correction signal that minimizes the difference between the phase change and the target value of the phase change.

Assignees

• Infineon Technologies Ag

Inventors

• Da Dalt Nicola
• Nonis Roberto
• Santa Thomas

Classifications

• H03K5/13 Primary

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H03K2005/00052

  by mixing the outputs of fixed delayed signals with each other or with the input signal · CPC title

• H03H11/20

  Two-port phase shifters providing an adjustable phase shift · CPC title