Buffer circuit having amplifier offset compensation and source driving circuit including the same

Patent metadata

Field	Value
Publication number	US-9577619-B2
Application number	US-201414546376-A
Country	US
Kind code	B2
Filing date	Nov 18, 2014
Priority date	Feb 5, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

Provided are an output buffer circuit having an amplifier offset compensation function and a source driving circuit including the output buffer circuit. The output buffer circuit may include a plurality of channel amplifiers, each of which is configured to adjust an amount of current flowing through transistors connected to at least one of a non-inverted input terminal and an inverted input terminal of a differential input unit to compensate an amplifier offset, and adjust buffer input voltage signals to generate output voltage signals.

First claim

What is claimed is:

1. An output buffer circuit, comprising:
a plurality of channel amplifiers, each of the channel amplifiers configured to adjust an amount of current flowing through at least one transistor connected to at least one of a non-inverted input terminal or an inverted input terminal of a differential input unit to compensate an amplifier offset, and each of the channel amplifiers configured to adjust buffer input voltage signals to generate output voltage signals,
wherein the output buffer is configured to measure an output voltage signal of each of the channel amplifiers in a state in which the non-inverted input terminal and the inverted input terminal are electrically connected to each other, and
compensate the amplifier offset using offset information at a time point at which the output voltage signal transitions.

2. The output buffer circuit of claim 1 , wherein the output buffer circuit is configured to adjust the amount of current flowing through the at least one transistor connected to the inverted input terminal of the differential input unit of each of the channel amplifiers such that the amplifier offset is compensated.

3. The output buffer circuit of claim 1 , wherein the output buffer circuit is configured to adjust the amount of current flowing through the at least one transistor connected to the non-inverted input terminal of the differential input unit of each of the channel amplifiers such that the amplifier offset is compensated.

4. The output buffer circuit of claim 1 , wherein each of the channel amplifiers comprises:
a differential input unit including a P-type differential input unit and an N-type differential input unit, the differential input unit configured to receive an input voltage signal and an output voltage signal in a differential mode and compensate the amplifier offset in response to a switch control signal;
an upper bias circuit electrically connected to the P-type differential input unit, the upper bias circuit configured to connect the P-type differential input unit to a supply voltage and to supply a first bias current to the P-type differential input unit;
a lower bias circuit electrically connected to the N-type differential input unit, the lower bias circuit configured to connect the N-type differential input unit to a ground voltage and supply a second bias current to the N-type differential input unit;
a load stage electrically connected to the differential input unit, the load stage configured to operate as a load of the differential input unit; and
an output stage electrically connected to the load stage, the output stage configured to connect an output of the load stage to the supply voltage or to the ground voltage.

5. The output buffer circuit of claim 4 , wherein the N-type differential input unit comprises:
a first NMOS transistor having a gate connected to the non-inverted input terminal of the differential input unit;
a second NMOS transistor having a gate connected to the inverted input terminal of the differential input unit; and
an amplifier offset compensating circuit connected in parallel to the second NMOS transistor, the amplifier offset compensating circuit configured to adjust the amount of current flowing through the at least one transistor connected to the inverted input terminal of the differential input unit in response to the switch control signal.

6. The output buffer circuit of claim 5 , wherein the amplifier offset compensating circuit comprises:
a third NMOS transistor connected in parallel to the second NMOS transistor;
a first switch connected between the gate of the second NMOS transistor and a gate of the third NMOS transistor; and
a second switch connected between the gate of the third NMOS transistor and the ground voltage.

7. The output buffer circuit of claim 4 , wherein the N-type differential input unit comprises:
at least one first NMOS transistor having a gate connected to the non-inverted input terminal of the differential input unit;
at least one second NMOS transistor having a gate connected to the inverted input terminal of the differential input unit; and
an amplifier offset compensating circuit connected in parallel to the at least one second NMOS transistor, the amplifier offset compensating circuit configured to adjust the amount of current flowing through the at least one transistor connected to the inverted input terminal of the differential input unit in response to the switch control signal.

8. The output buffer circuit of claim 7 , wherein the amplifier offset compensating circuit comprises:
at least one third NMOS transistor connected in parallel to the at least one second NMOS transistor;
at least one first switch connected between a gate of each of the at least one third NMOS transistor and the gate of the at least one second NMOS transistor; and
at least one second switch connected between the gate of the at least one third NMOS transistor and the ground voltage.

9. The output buffer circuit of claim 4 , wherein the N-type differential input unit comprises:
at least one first NMOS transistor having a gate connected to the inverted input terminal of the differential input unit;
at least one second NMOS transistor having a gate connected to the non-inverted input terminal of the differential input unit; and
an amplifier offset compensating circuit connected in parallel to the at least one second NMOS transistor, the amplifier offset compensating circuit configured to adjust the amount of current flowing through the at least one transistor connected to the non-inverted input terminal of the differential input unit in response to the switch control signal.

10. The output buffer circuit of claim 7 , wherein the amplifier offset compensating circuit comprises:
at least one third NMOS transistor connected in parallel to the second NMOS transistor;
a first switch connected between a gate of the third NMOS transistor and the gate of the second NMOS transistor; and
a second switch connected between the gate of the third NMOS transistor and the ground voltage.

11. The output buffer circuit of claim 4 , wherein each of the channel amplifiers further comprises:
a switch control signal generating circuit configured to generate the switch control signal based on offset information.

12. The output buffer circuit of claim 1 , wherein each of the channel amplifiers includes a P-type differential input unit, an N-type differential input unit, and an amplifier offset compensating circuit, the amplifier offset compensating circuit configured to adjust the amount of the current flowing through the at least one transistor connected to the at least one of the non-inverted input terminal or the inverted input terminal of the differential input unit in response to the switch control signal.

13. A gamma voltage generator, comprising:
a plurality of amplifiers; and
string resistors,
wherein the gamma voltage generator is configured to,
detect an offset of each of the amplifiers,
determine polarities of the amplifiers, and
provide the determined polarities to the amplifiers to perform a chopping operation, and

the gamma voltage generator is further configured to,
measure an output voltage signal of each of the amplifiers in a state in which the non-inverted input terminal and the inverted input terminal are electrically connected to each other, and
compensate the offset of each of the amplifiers using offset information at a time point at which the output voltage signal transitions.

14. The gamma voltage generator of claim 13 , comprising:
a gamma voltage generating unit including the plurality of ampl

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyung-Tae
• Jung Ji-Woon
• Kim In-Suk
• Bae Jong-Kon
• Woo Jae-Hyuck
• Kang Won-Sik
• Kim Yang-Hyo

Classifications

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03K5/003 Primary

  Changing the DC level (reinsertion of DC component of a television signal H04N5/16) · CPC title

• H03F3/3022 Primary

  CMOS common source output SEPP amplifiers (H03F3/3008 takes precedence) · CPC title

• H03F3/45112

  Complementary long tailed pairs having parallel inputs and being supplied in parallel · CPC title

• H03F2203/45212

  the differential amplifier being designed to have a reduced offset · CPC title