Emulated peak current limit scheme for switching regulator

Patent metadata

Field	Value
Publication number	US-9577509-B2
Application number	US-201414260690-A
Country	US
Kind code	B2
Filing date	Apr 24, 2014
Priority date	Mar 27, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

An apparatus comprises a switching circuit, an error amplifier circuit, a current threshold circuit, and an over-current detection circuit. The switching circuit provides a switching duty cycle that includes a charge portion and a discharge portion. The error amplifier circuit generates an error signal representative of a difference between a target voltage value and a voltage at an output of the voltage regulator circuit. The switching circuit adjusts the switching duty cycle to regulate the voltage at the output using the error signal and a reference waveform signal. The current threshold circuit generates an adaptive peak current limit threshold. The over-current detection circuit generates an over-current signal when the reference waveform signal satisfies the adaptive peak current limit threshold during the charging portion of the switching cycle. The switching circuit interrupts one or more switching cycles when the reference waveform signal satisfies the adaptive peak current limit threshold.

First claim

What is claimed is:

1. A voltage regulator circuit comprising:
a switching circuit configured to provide a switching duty cycle that includes a charge portion and a discharge portion for charging and discharging an inductor;
an error amplifier circuit configured to generate an error signal representative of a difference between a target voltage value and a voltage at an output of the voltage regulator circuit, wherein the switching circuit is configured to adjust the switching duty cycle to regulate the voltage at the output using the error signal and a reference waveform signal;
a current threshold circuit configured to emulate inductor current using a valley current limit threshold voltage value and a peak-to-peak voltage value of the reference waveform signal and generate an adaptive peak current limit threshold using the emulated current; and
an over-current detection circuit configured to generate an over-current signal when the reference waveform signal satisfies the adaptive peak current limit threshold during the charging portion of the switching cycle, and wherein the switching circuit is configured to interrupt the charge portion of one or more switching cycles when the reference waveform signal satisfies the adaptive peak current limit threshold.

2. The voltage regulator circuit of claim 1 ,
wherein the reference waveform circuit includes a current source electrically coupled to a first capacitor to recurrently charge the first capacitor to generate an increasing voltage ramp signal,
wherein the current threshold circuit includes a second capacitor and a current mirror circuit configured to mirror current of the current source of the reference waveform circuit and to regenerate the increasing voltage ramp signal of the reference waveform circuit, and
wherein the summing circuit node is configured to sum the voltage value of the peak of the regenerated increasing voltage ramp signal and the valley current limit threshold voltage value as the adaptive peak current limit threshold.

3. The voltage regulator circuit of claim 1 , wherein the current threshold circuit includes a filter circuit configured to filter the generated adaptive peak current limit threshold, and wherein the over-current protection circuit is configured to compare the filtered adaptive peak current limit threshold to the reference waveform signal.

4. The voltage regulator circuit of claim 1 , including:
an inductor electrically coupled to the switching circuit;
a reference waveform circuit; and
a current sensing circuit electrically coupled to the switching circuit and the reference waveform circuit,
wherein the switching circuit includes a high-side switch circuit and a low-side switch circuit, and wherein the switching circuit is configured to charge the inductor by activation of the high-side switch during the charge portions of the switching duty cycle, discharge the inductor by activation of the low side switch during the discharge portion of the switching duty cycle,
wherein the current sensing circuit is configured to generate a voltage signal representative of inductor current at the low side switch circuit during the discharge portion of the switching cycle, and
wherein the reference waveform circuit is configured to incorporate the generated voltage signal representative of the sensed inductor current into the reference waveform signal.

5. The voltage regulator circuit of claim 1 , including:
an inductor electrically coupled to the switching circuit,
wherein the current sensing circuit is configured to generate a decreasing voltage ramp signal representative of inductor current during the discharge portion of the switching duty cycle,
wherein a reference waveform circuit includes a current source electrically coupled to a capacitor to recurrently charge the capacitor to generate an increasing voltage ramp signal, and wherein the reference waveform circuit is configured to incorporate the increasing voltage ramp signal and the decreasing voltage ramp signal into a substantially sawtooth reference waveform signal.

6. The voltage regulator circuit of claim 1 , wherein the switching circuit includes one or more logic circuits to implement pulse width modulation switching (PWM) and wherein the target voltage value is less than a voltage at an input of the voltage regulator circuit.

7. The voltage regulator circuit of claim 1 , wherein the current threshold circuit includes:
a reference circuit configured to provide the valley current limit threshold voltage value;
a sample and hold circuit configured to generate the voltage value corresponding to a peak-to-peak value of the reference waveform signal; and
a summoning circuit node to sun the peak-to-peak value of the reference waveform signal and the valley current limit threshold voltage value as the adaptive peak current limit threshold.

8. A voltage regulating system comprising:
a switching circuit configured to provide PWM regulation using a switching duty cycle that includes a charge portion and a discharge portion for charging and discharging an inductor;
a feedback circuit configured to generate an error signal representative of a difference between a target voltage value and a voltage at an output of the voltage regulating system, wherein the switching circuit is configured to modulate the switching duty cycle using a comparison of the error signal and a reference waveform signal;
a current threshold circuit configured to emulate inductor current using a valley current limit threshold voltage value and a peak-to-peak voltage value of the reference waveform signal and generate an adaptive peak current limit threshold using the emulated current; and
an over-current detection circuit configured to generate an over-current signal when the reference waveform signal satisfies the adaptive peak current limit threshold, and wherein the switching circuit is configured to interrupt one or more switching duty cycles when the reference waveform signal satisfies the adaptive peak current limit threshold.

9. The voltage regulating system of claim 8 , wherein the current threshold circuit includes:
a reference circuit configured to provide the valley circuit limit threshold voltage value;
a sample and hold circuit configured to generate the voltage value corresponding to a peak-to-peak value of the reference waveform signal; and
a summing circuit node to sum the peak-to-peak value of the reference waveform signal and the valley current limit threshold voltage value as the adaptive peak current limit threshold.

10. The voltage regulating system of claim 9 ,
wherein the reference waveform circuit includes a current source electrically coupled to a first capacitor to recurrently charge the first capacitor to generate an increasing voltage ramp signal,
wherein the current threshold circuit includes a second capacitor and a current mirror circuit configured to mirror current of the current source of the reference waveform circuit and to regenerate the increasing voltage ramp signal of the reference waveform circuit,
wherein the summing circuit node is configured to sum the voltage value of the peak of the regenerated increasing voltage ramp signal and the valley current limit threshold voltage value as the adaptive peak current limit threshold.

11. The voltage regulating system of claim 10 , wherein the sample and hold circuit includes a third capacitor configured to sample the regenerated increasing voltage ramp signal and fourth capacitor to hold the voltage value of the peak of the regenerated increasing voltage ramp signal.

12. The voltage regulating system of claim 9 , including a filter circuit configured to filter a si

Assignees

• Analog Devices Global

Inventors

• Wang Basa
• Zhu Zhijie

Classifications

• H02M1/32 Primary

  Means for protecting converters other than automatic disconnection · CPC title

• H02M2001/0009

  Electricity · mapped topic

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title