NMOS LDO PSRR improvement using power supply noise cancellation

Patent metadata

Field	Value
Publication number	US-9577508-B2
Application number	US-201313894589-A
Country	US
Kind code	B2
Filing date	May 15, 2013
Priority date	May 15, 2013
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

Power-supply ripple rejection (PSRR) at high frequencies is improved for an LDO voltage regulator with an NMOS pass transistor (MN 1 ). A ripple voltage (V ripple ) present on the input voltage causes a ripple current (I ripple ) through parasitic gate-drain capacitance of the pass transistor. A small ripple current (I fraction ) proportional to the ripple current (I ripple ) is generated and amplified to generate a cancellation current (I cancel ). The cancellation current is drawn from the gate of NMOS pass transistor (MN 1 ) to cancel the ripple current so that no net ripple current flows through the finite output impedance of an error amplifier ( 2 ), to thereby achieve the PSRR improvement.

First claim

What is claimed is:

1. A low dropout (LDO) voltage regulator having a supply voltage input and a regulated voltage output, comprising:
an error amplifier having an output connected to a first conductor, an N-channel pass transistor having a drain coupled to the supply voltage input, a source coupled to the regulated voltage output, and a gate coupled to the first conductor, the error amplifier having a first input coupled to a reference voltage and a second input coupled via a feedback path to the regulated voltage output, a ripple voltage signal present on the supply voltage input producing a ripple current which tends to flow into an output impedance of the error amplifier and generate a corresponding ripple voltage on the gate of the pass transistor;
an N-channel cancellation transistor having a drain coupled to the supply voltage input and a source coupled to the regulated voltage output and having a gate coupled to a second conductor distinct from the first conductor, for producing an AC injection cancellation current which is a predetermined proportion of the ripple current;
biasing circuitry coupled between the first conductor and the second conductor for biasing the gate of the N-channel cancellation transistor at a voltage having a predetermined relationship to a voltage on the first conductor;
an AC current gain circuit; and
circuitry for coupling the second conductor to an input of the AC current gain circuit, the AC current gain circuit having an output coupled to the first conductor and operating to multiply the AC injection cancellation current sufficiently to generate a ripple cancellation current substantially equal to the ripple current in a direction opposite to the ripple current to cancel the ripple current in the first conductor so as to prevent the ripple current from flowing into the output impedance of the error amplifier, wherein the power supply rejection ratio (PSRR) of the LDO regulator is improved.

2. The low dropout voltage regulator of claim 1 wherein the predetermined proportion of the ripple current is 1 percent.

3. The low dropout voltage regulator of claim 2 wherein the gain of the AC current gain circuit is 100.

4. The low dropout voltage regulator of claim 1 wherein the AC current gain circuit includes a first current mirror circuit having an input coupled to the input of the AC current gain circuit and an output coupled to an input of a second current mirror circuit, the second current mirror circuit having an output coupled to the first conductor.

5. The low dropout voltage regulator of claim 4 wherein the first current mirror circuit includes an NPN input transistor having a collector coupled to the input of the AC current gain circuit and a gate of an N-channel transistor, an emitter coupled to the second reference voltage, and a base coupled to a base of an NPN output transistor and a source of the N-channel transistor, the NPN output transistor having an emitter coupled to the second reference voltage through both a third resistor and a first capacitor and a collector coupled to an input of a current mirror including an output coupled to the input.

6. The low dropout voltage regulator of claim 5 wherein the second current mirror circuit is substantially similar to the first current mirror circuit.

7. The low dropout voltage regulator of claim 1 wherein the biasing circuitry includes a first voltage follower having an input coupled to the first conductor and a second voltage follower having an input coupled to an output of the first voltage follower.

8. The low dropout voltage regulator of claim 7 wherein the first voltage follower circuit includes an NPN transistor having a collector coupled to a first reference voltage, a base coupled to the first conductor, and wherein the second voltage follower includes a PNP transistor having an emitter coupled to the second conductor and a second current source, a base coupled to an emitter of the NPN transistor, and a collector coupled to the input of the AC current gain circuit.

9. The low dropout voltage regulator of claim 8 wherein the coupling circuitry includes the PNP transistor.

10. The low dropout voltage regulator of claim 9 wherein the feedback path includes a first resistor coupled between the second input of the error amplifier and a second reference voltage and a second resistor coupled between the second input of the error amplifier and the regulated voltage output.

11. The low dropout voltage regulator of claim 1 wherein the biasing circuitry includes a buffer circuit.

12. The low dropout voltage regulator of claim 1 wherein the predetermined proportion of the ripple current is in the range from approximately 1 percent to approximately 2 percent.

13. The low dropout voltage regulator of claim 1 wherein the biasing circuitry biases the gate of the N-channel cancellation transistor to a voltage which is equal to the voltage on the first conductor and the gate of the pass transistor.

14. A method for canceling the effect of a ripple voltage present on a supply voltage input from a regulated voltage output of a low dropout (LDO) voltage regulator, the method comprising:
providing an error amplifier having an output connected to a first conductor, an N-channel pass transistor having a drain coupled to the supply voltage input, a source coupled to the regulated voltage output, and a gate coupled to the first conductor, the error amplifier having a first input coupled to a reference voltage and a second input coupled via a feedback path to the regulated voltage output, a ripple voltage signal present on the supply voltage input producing a ripple current which tends to flow into an output impedance of the error amplifier and generate a corresponding ripple voltage on the gate of the pass transistor;
coupling a drain of an N-channel cancellation transistor to the supply voltage input and a source coupled to the regulated voltage output and coupling a gate of the N-channel cancellation transistor to a second conductor distinct from the first conductor, for producing an AC injection cancellation current which is a predetermined proportion of the ripple current;
biasing the gate of the N-channel cancellation transistor at a voltage that is substantially equal to the voltage of the first conductor; and
multiplying the AC injection cancellation current sufficiently to generate a ripple cancellation current in the first conductor substantially equal to the ripple current in a direction opposite to the ripple current to cancel the ripple current in the first conductor so as to prevent the ripple current from flowing into the output impedance of the error amplifier and from thereby causing a ripple voltage to be coupled onto the regulated voltage output, wherein the power supply rejection ratio (PSRR) of the LDO regulator is improved.

15. The method of claim 14 wherein step (c) includes providing biasing circuitry including a first voltage follower having an input coupled to the first conductor and a second voltage follower having an input coupled to an output of the first voltage follower and also having an output coupled to the first conductor.

16. The method of claim 15 wherein the first voltage follower circuit includes an NPN transistor having a collector coupled to a first reference voltage, a base coupled to the first conductor and an emitter coupled to a first current source, and wherein the second voltage follower includes a PNP transistor having an emitter coupled to the second conductor and a second current source, a base coupled to the emitter of the NPN transistor, and a collector coupled to the inp

Assignees

• Texas Instruments Inc

Inventors

• Wang Jianbao

Classifications

• H02M1/15 Primary

  using active elements · CPC title

• H02M2001/0022

  Electricity · mapped topic

• G05F1/575

  characterised by the feedback circuit · CPC title

• H02M1/0022

  the disturbance parameters being input voltage fluctuations · CPC title