Beam forming system having linear samplers

Patent metadata

Field	Value
Publication number	US-9577328-B2
Application number	US-201414256216-A
Country	US
Kind code	B2
Filing date	Apr 18, 2014
Priority date	Apr 18, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A frequency conversion circuit having a plurality of N signal channels, each being fed an input signal and a train of pluses having a period T and a duty cycle T/N. Each channel includes: a sampler coupled the input signal and being responsive to sampling signals; and a controllable time delay for producing the train of sampling signals in response to the train of pulses, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay. Each one of the sampling signals is produced by the time delay in each one of the channels with the period T and the duty cycle T/N with the sampling signals in one of the trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains the sampling signals a time T/N.

First claim

What is claimed is:

1. A frequency conversion/time delay circuit, fed by an input signal having a frequency to be frequency converted to a converted frequency, the frequency conversion/time delay circuit, comprising:
a plurality of N signal channels, where N is an integer, each one of the plurality of N signal channels being fed the input signal; a periodic signal having a period T related to the converted frequency and a duty cycle TN; and a time delay signal, each one of the plurality of N signal channels comprising:
(a) a sampler fed by the input signal and responsive to the periodic signal for producing a train of sampling pulses; and
(b) a controllable time delay circuit, fed by a time delay signal, for producing the train of sampling pulses in response to the periodic signal, the time delay circuit imparting a time delay to the train of sampling pulses in accordance with the time delay signal fed to the time delay circuit;

wherein the train of sampling pulses in each one of the N signal channels is produced in accordance with the time delay signal fed to such one of the N signal channels, the train of sampling pulses in one of the N signal channels being delayed with respect to the train of sampling pulses in another one of the N signal channels a time T/N.

2. A frequency conversion/time delay circuit, fed by an input signal having a frequency to be frequency converted to a converted frequency, the frequency conversion circuit, comprising:
(A) a plurality of N, where N is an integer, signal channels, each one of the N signal channels being fed by the input signal and a periodic signal having a period T related to the converted frequency and a duty cycle T/N; and a time delay signal, each one of the N signal channels comprising:
(i) a sampler fed by the input signal and being responsive to a train of sampling pulses fed thereto;
(ii) a controllable time delay circuit fed by the delay signal for producing the train of sampling pulses to the sampler in such one of the signal N channels in response to the periodic signal, the controllable time delay circuit imparting a time delay to the train of sampling pulses in accordance with the time delay signal fed to the controllable time delay circuit; and

(B) wherein the train of sampling pulses in the N trains of sampling pulses produced by the controllable time delay circuit in one of the N signal channels is delayed with respect to the sampling pulses in another one of the N signal channels a time T/N in accordance with the time delay signal.

3. A frequency conversion/time delay circuit, comprising:
an input port for receiving an input signal having a frequency to be frequency converted to a converted frequency;
a source of a plurality of N time delay control signals, where N is an integer;
a plurality of N samplers;
a plurality of N controllable time delay circuits, each one of the N controllable time delay circuits being fed a corresponding one of the N time delay control signals;
a source for producing a train of pulses having a period T and a duty cycle T/N, the train of pulses being fed in common to the plurality of N controllable time delay circuits;
a plurality of N signal channels, where N is an integer, each one of the N signal channels being fed to the input port for carrying a corresponding portion of the input signal having the frequency to be frequency converted, each one of the signal channels having:
(i) a corresponding one of the N samplers, each one of the N samplers being fed the corresponding portion of the input signal; and
(ii) a corresponding one of the N controllable time delay circuits; each one of the N controllable time delay circuits delaying the train of pulses fed thereto in accordance with the one corresponding one of the N time delay control signals fed thereto, each one of the N controllable time delay circuits providing a corresponding one of N trains of sampling signals, each one of the N trains of sampling signals being fed to a corresponding one of the N samplers with each one of the sampling signals in the N trains of sampling signals having a period T and a duty cycle T/N, and with the sampling signals in one of the N trains of the sampling signals being delayed with respect to the sampling signals in another one of the N trains a time T/N.

4. A phased array antenna system, comprising:
(A) a beam steering computer;
(B) a plurality M, where M is an integer, of antenna elements each one being fed to a corresponding one of a plurality of M antenna ports;
(C) a pulse train source, the pulses in the train having a period T, and a duty cycle T/N;
(D) a plurality of M frequency conversion/variable time delay circuits, each one of the M frequency conversion/variable time delay circuits being fed to a corresponding one of the M antenna ports, each one of the M frequency conversion/variable time delay circuits, comprising:
a plurality of N, where N is an integer, signal channels, each one of the N signal channels being fed to the corresponding one of the one of the M antenna ports, each one of the signal channels having:
a sampler coupled to said corresponding one of the one of the M antenna ports and responsive to sampling signals fed thereto;
a controllable time delay circuit for producing the train of sampling signals to the sampler in such one of the signal channels in response to a train of pulses fed to the controllable time delay circuit in such one of the signal channels, the controllable time delay circuit imparting a time delay δ to the pulses in the train of pulses fed to the controllable time delay circuit in such one of the signal channels in accordance with a time delay command signal fed to the controllable time delay circuit by the beam seeing computer; and

(E) wherein each one of the sampling signals in the N trains of sampling signals are produced by the controllable time delay circuit in each one of the channels with a period T and a duty cycle T/N with the sampling signals in one of the N trains of the sampling signals being delayed with respect to the sampling signals in another one of the N trains of sampling signals a time T/N.

Assignees

• Raytheon Co

Inventors

• Morton Matthew A
• Comeau Jonathan P
• Kopa Anthony

Classifications

• H01Q3/2682 Primary

  Time delay steered arrays · CPC title

• H03D2200/006

  Signal sampling · CPC title

• H03D7/165

  at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature (combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002) · CPC title

• H03D7/00

  Transference of modulation from one carrier to another, e.g. frequency-changing (H03D9/00, H03D11/00 take precedence; dielectric amplifiers, magnetic amplifiers, parametric amplifiers used as a frequency-changers H03F) · CPC title