Wireless interconnect for an integrated circuit

Patent metadata

Field	Value
Publication number	US-9577322-B2
Application number	US-200913124291-A
Country	US
Kind code	B2
Filing date	Oct 20, 2009
Priority date	Oct 21, 2008
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A wireless interconnect for an integrated circuit and a method of making the wireless interconnect. The interconnect includes a first antenna and a second antenna arranged over a plurality of electrically conductive interconnects. The interconnect also includes a propagation layer. The first and second antennae are arranged in between the propagation layer and the electrically conductive interconnects.

First claim

The invention claimed is:

1. A wireless interconnect for an integrated circuit, the wireless interconnect comprising:
a first antenna and a second antenna arranged over a plurality of electrically conductive interconnects; and
a propagation layer configured to allow signals to propagate between the first antenna and the second antenna, wherein the first and second antennae are arranged in between the propagation layer and the electrically conductive interconnects, the electrically conductive interconnects and the first and second antennae are provided on a first wafer or die, and the electrically conductive interconnects are arranged in between the first and second antennae and a semiconductor substrate of the first wafer or die.

2. The wireless interconnect of claim 1 , wherein the propagation layer comprises a semiconductor material.

3. The wireless interconnect of claim 2 , wherein the propagation layer comprises a semiconductor substrate of a die or wafer.

4. The wireless interconnect of claim 3 , wherein the propagation layer comprises a semiconductor substrate of a second wafer or die.

5. The wireless interconnect of claim 1 , wherein the first and second antennae and the electrically conductive interconnects are arranged within a common layer of material.

6. The wireless interconnect of claim 1 , wherein the first and second antennae are dipole antennae.

7. The wireless interconnect of claim 1 , wherein the electrically conductive interconnects are arranged in a plurality of levels.

8. An integrated circuit comprising the wireless interconnect of claim 1 .

9. A method of making a wireless interconnect for an integrated circuit, the method comprising:
arranging a first antenna and a second antenna over a plurality of electrically conductive interconnects; and
providing a propagation layer over the first and second antennae, such that the first and second antennae are arranged in between the propagation layer and the electrically conductive interconnects;
arranging the electrically conductive interconnects over a semiconductor substrate of the first wafer or die, and
arranging the first and second antennae over the electrically conductive interconnects opposite the semiconductor substrate of the first wafer or die.

10. The method of claim 9 , wherein the propagation layer comprises a semiconductor material.

11. The method of claim 10 , wherein the propagation layer comprises a semiconductor substrate of a die or wafer.

12. The method of claim 11 , further comprising:
stacking a second wafer or die over the first wafer or die to arrange a semiconductor substrate of the second wafer or die over the first and second antennae.

13. The method of claim 9 , comprising:
forming the plurality of electrically conductive interconnects and the first and second antennae using aluminum or damascene processing.

14. The method of claim 9 comprising:
arranging the first and second antennae and the electrically conductive interconnects within a common layer of material.

15. The method of claim 9 , comprising:
forming the plurality of electrically conductive interconnects using a damascene process, and providing the first and second antennae in a passivation layer over the electrically conductive interconnects.

16. The method of claim 9 , comprising:
arranging the electrically conductive interconnects in a plurality of levels.

17. The method of claim 10 , further comprising:
incorporating the wireless interconnect into an integrated circuit.

18. The method of claim 11 , wherein the propagation layer is only provided above a portion of the die that incorporates the antennae.

Assignees

• Hoofman Romano
• Nxp Bv

Inventors

• Hoofman Romano

Classifications

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W44/248

  for antennas · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title