Low cost demos transistor with improved CHC immunity

Patent metadata

Field	Value
Publication number	US-9577094-B2
Application number	US-201514885637-A
Country	US
Kind code	B2
Filing date	Oct 16, 2015
Priority date	Dec 30, 2013
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a DEMOS transistor further including:
a body of the DEMOS transistor formed by a well in a substrate of the integrated circuit wherein the body has a first conductivity type;
a lightly doped extended drain of the DEMOS transistor wherein the lightly doped extended drain has a second conductivity type opposite the first conductivity type;
a gate of the DEMOS transistor wherein a first portion of the gate overlies the body of the DEMOS transistor and a second portion of the gate overlies a portion of the lightly doped extended drain adjacent to the body;
a reduced resistance surface channel of the second conductivity type in the lightly doped extended drain under the gate;
a reduced resistance subsurface channel of the second conductivity type in the lightly doped extended drain that is not under the gate; and
a reduced resistance transition channel of the second conductivity type that couples the reduced resistance surface channel to the reduced resistance subsurface channel.

2. The integrated circuit in claim 1 , wherein the second conductivity type is p-type, the first conductivity type is n-type, and the DEMOS transistor is a DEPMOS transistor.

3. The integrated circuit in claim 1 , wherein the second conductivity type is n-type, the first conductivity type is p-type, and the DEMOS transistor is a DENMOS transistor.

4. The integrated circuit in claim 1 further comprising a low voltage NMOS transistor.

5. The integrated circuit of claim 1 further comprising a low voltage PMOS transistor.

6. The integrated circuit of claim 1 further comprising a low voltage NMOS and a low voltage PMOS transistor.

7. A process of forming an integrated circuit, comprising the steps:
forming a well of a second dopant type in a substrate of a first conductivity type;
forming a lightly doped extended drain of the first dopant type;
forming DEMOS gate and gate dielectric on the substrate, wherein a first portion of the DEMOS gate overlies the well and a second portion of the DEMOS gate overlies a first portion of the lightly doped extended drain;
forming an implant pattern on the first portion of the DEMOS gate;
using the implant pattern, implanting a dopant of the first doping type through the second portion of the DEMOS gate to form a reduced resistance surface channel under the second portion of the DEMOS gate and into the lightly doped extended drain to form a reduced resistance subsurface channel in a portion of the lightly doped extended drain that is not under the DEMOS gate, wherein the implanting also forms a reduced resistance transition channel which couples the reduced resistance surface channel to the reduced resistance subsurface channel under a drain end of the DEMOS transistor gate.

8. The process of claim 7 , wherein the substrate doping is p-type, the well doping is n-type and the doping of the lightly doped extended drain is p-type and the DEMOS transistor is a DEPMOS transistor.

9. The process of claim 7 , wherein the substrate doping is n-type, the well doping is p-type and the doping of the lightly doped extended drain is n-type and the DEMOS transistor is a DENMOS transistor.

10. The process of claim 7 , wherein the implanting is at an angle of between 5 degrees and 30 degrees.

11. The process of claim 7 , wherein the implanting is at an angle of 15 degrees.

12. The process of claim 7 further comprising the steps:
forming a first low voltage gate of a first transistor over the substrate; and
forming a second low voltage gate of a second transistor over the well;
wherein the implanting also implants the dopant into the substrate to set the turn on voltage of the first transistor; and
wherein the implanting also implants into the well to set the turn on voltage of the second transistor.

13. The process of claim 12 , wherein the DEMOS transistor is DEPMOS, the first transistor is a low voltage NMOS transistor and the second transistor is a low voltage PMOS transistor.

14. The process of claim 12 , wherein the DEMOS transistor is DENMOS, the first transistor is a low voltage PMOS transistor and the second transistor is a low voltage NMOS transistor.

Assignees

• Texas Instruments Inc

Inventors

• Tang Shaoping
• Chatterjee Amitava
• Khan Imran Mahmood
• Liu Kaiping

Classifications

• H10P50/264

  by chemical means · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/212

  Through-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10D64/01322

  the conductor contacting the insulator having a lateral variation in doping, composition or deposition steps · CPC title