Structures and methods of fabricating dual gate devices

Patent metadata

Field	Value
Publication number	US-9577089-B2
Application number	US-201113039089-A
Country	US
Kind code	B2
Filing date	Mar 2, 2011
Priority date	Mar 2, 2010
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

First claim

What is claimed is:

1. A method of fabricating a dual gate semiconductor device, said method comprising:
depositing oxide into a first trench and into a second trench that are formed in a substrate, said oxide also deposited over a mesa that is between said first trench and said second trench;
depositing first polysilicon into said first trench and into said second trench;
performing a first polysilicon polishing process to planarize the exposed upper surfaces of said first polysilicon so that, after said first polysilicon polishing process, exposed surfaces of said first polysilicon are flush with the surface of said oxide;
after said polysilicon polishing process, performing an oxide polishing process to remove said oxide from over said mesa and further remove part of said first polysilicon so that, after said oxide polishing process, exposed surfaces of said first polysilicon are flush with said mesa;
after said first polysilicon polishing process, forming a third trench in said substrate between said first and second trenches, wherein said third trench is shallower than said first and second trenches;
depositing second polysilicon into said third trench;
performing a second polysilicon polishing process to planarize an exposed surface of said second polysilicon so that said surface is flush with adjacent surfaces; and
forming a first metal contact to said first polysilicon and a second metal contact to said second polysilicon.

2. The method of claim 1 wherein said first and second polysilicon polishing processes and said oxide polishing process comprise chemical mechanical polishing processes.

3. The method of claim 1 wherein said first metal contact is directly over and in contact with said first polysilicon, and said second metal contact is directly over and in contact with said second polysilicon.

4. The method of claim 1 wherein said first metal contact is part of a first metal layer and said second metal contact is part of a second metal layer, wherein said first and second metal layers are in the same surface plane but are physically isolated from one another.

5. The method of claim 1 wherein said third trench is wider than said second metal contact.

6. The method of claim 1 wherein said first, second, and third trenches are parallel to one another.

7. The method of claim 1 wherein said first metal contact is at a first end of said first trench and at a first end of said second trench, and wherein said second metal contact is at a first end of said third trench, wherein said first end of said third trench is at the opposite end of said third trench relative to said first end of said first trench and said first end of said second trench.

8. The method of claim 7 wherein said first end of said third trench is wider than a second end of said third trench.

9. The method of claim 1 wherein said exposed surfaces of said first polysilicon after said oxide polishing process is performed and said surface of said second polysilicon after said second silicon polishing process is performed are flush with surfaces of mesas between said first, second, and third trenches.

10. The method of claim 1 wherein said first and second trenches are lined with first oxide layers and said third trench is lined with a second oxide layer, wherein surfaces of said first oxide layers and said second oxide layer are flush with said exposed surfaces of said first polysilicon after said oxide polishing process is performed and said exposed surface of said second polysilicon after said second polysilicon polishing process is performed.

11. A method of fabricating a dual gate semiconductor device, said method comprising:
forming a first trench and a second trench in a substrate, said first and second trenches separated by a first mesa;
forming a first oxide layer inside said first and second trenches and over said first mesa, and then depositing first polysilicon into said first and second trenches;
performing a first polysilicon polishing process to remove at least some of said first polysilicon;
after said first polysilicon polishing process id performed, etching back the exposed upper surface of said first polysilicon so that it is recessed relative to said first oxide layer over said first mesa;
after said etching, performing an oxide polishing process to remove said first oxide layer from over said first mesa and any portion of said exposed upper surface of said first polysilicon protruding above said first mesa so that, after said oxide polishing process is performed, exposed surfaces of said first polysilicon are flush with said first mesa;
after said first polysilicon polishing process and after said oxide polishing process are performed, forming a third trench in said first mesa between said first and second trenches, said first and third trenches separated by a second mesa and said second and third trenches separated by a third mesa, wherein said third trench is shallower than said first and second trenches;
forming a second oxide layer inside said third trench and over said second and third mesas, and then depositing second polysilicon into said third trench; and
performing a second polysilicon polishing process to remove at least some of said second polysilicon.

12. The method of claim 11 further comprising forming a first metal contact to said first polysilicon and a second metal contact to said second polysilicon.

13. The method of claim 12 wherein said first metal contact is directly over and in contact with said first polysilicon and said second metal contact is directly over and in contact with said second polysilicon in said second trench.

14. The method of claim 12 wherein said first metal contact is part of a first metal layer and said second metal contact is part of a second metal layer, wherein said first and second metal layers are in the same surface plane but are physically isolated from one another.

15. The method of claim 12 wherein said second metal contact is narrower than said third trench.

16. The method of claim 11 wherein said first and second polysilicon polishing processes and said oxide polishing process comprise chemical mechanical polishing processes.

17. The method of claim 11 wherein said oxide polishing process further comprises depositing additional oxide prior to oxide polishing.

Assignees

• Terrill Kyle
• Pattanayak Deva
• Luo Zhiyun
• Vishay Siliconix

Inventors

• Terrill Kyle
• Bai Yuming
• Pattanayak Deva
• Luo Zhiyun

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10D64/2523

  for vertical devices wherein the source or drain electrodes extend entirely through semiconductor bodies · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title