Method for fabricating semiconductor device having dual work function gate structure

Patent metadata

Field	Value
Publication number	US-9577052-B2
Application number	US-201615058933-A
Country	US
Kind code	B2
Filing date	Mar 2, 2016
Priority date	Dec 16, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A semiconductor device includes a body including a first junction region; a pillar positioned over the body, and including a vertical channel region and a second junction region over the vertical channel region; a gate trench exposing side surfaces of the pillar; a gate dielectric layer covering the gate trench; and a gate electrode embedded in the gate trench, with the gate dielectric layer interposed therebetween. The gate electrode includes a first work function liner overlapping with the vertical channel region, and including an aluminum-containing metal nitride; a second work function liner overlapping with the second junction region, and including a silicon-containing non-metal material; and an air gap positioned between the second work function liner and the second junction region.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a pillar;
forming a gate dielectric layer over a lower side surface and over an upper side surface of the pillar;
forming a gate electrode including a first work function liner over the lower side surface of the pillar;
forming a second work function liner over the upper side surface of the pillar,
forming a gap between the second work function liner and the upper side surface of the pillar;
capping the gap to form an air gap; and
forming a junction region in the pillar to have a depth that overlaps with the air gap and the second work function liner,
wherein the air gap is provided between the junction region and the second work function liner.

2. The method according to claim 1 , wherein the forming of the pillar comprises:
preparing a substrate;
etching the substrate to form a line type active region;
patterning the line type active region to form an island type active region;
etching the island type active region to form a preliminary pillar; and
etching the preliminary pillar to form the pillar.

3. The method according to claim 1 , wherein the forming of the gate electrode comprises:
forming a preliminary first work function liner over the lower side surface and the upper side surface of the pillar;
forming the second work function liner over the preliminary first work function liner; and
recessing the preliminary first work function liner to form the first work function liner, wherein the first work function liner does not extend over the second work function liner.

4. The method according to claim 1 , wherein the first work function liner includes titanium aluminum nitride.

5. The method according to claim 1 , wherein the second work function liner includes an N-type impurity-doped polysilicon.

6. The method according to claim 1 , wherein the forming of the gate electrode comprises:
forming a first work function liner layer over the gate dielectric layer;
etching the first work function liner layer to form a preliminary first work function liner which is positioned on the lower side surface of the pillar;
forming a first low resistivity electrode over the preliminary first work function liner and at a level lower than a top surface of the pillar;
forming a second work function liner layer at a level higher than the first low resistivity electrode and the preliminary first work function liner;
forming a second low resistivity layer over the second work function liner layer;
recessing the second low resistivity layer and the second work function liner layer to form a second low resistivity electrode and the second work function liner at a level lower than the top surface of the pillar; and
recessing the preliminary first work function liner to non-overlap with the first work function liner, and forming the first work function liner and the gap.

7. The method according to claim 6 , wherein the second low resistivity electrode is formed of a material which is non-reactive with the second work function liner,
wherein the first low resistivity electrode is formed of a fluorine-free material,
wherein the first low resistivity electrode is formed of a material which is non-reactive with the second work function liner.

8. The method according to claim 6 , wherein the first low resistivity electrode is formed of a material which is non-reactive with the second work function liner, and
wherein the second low resistivity electrode is formed of a material which is reactive with the second work function liner.

9. The method according to claim 6 , further comprising:
forming an upper barrier which is positioned between the second work function liner and the second low resistivity electrode.

10. The method according to claim 6 , further comprising:
forming a lower barrier which is positioned between the first work function liner and the first low resistivity electrode; and
forming an upper barrier which is positioned between the second work function liner and the second low resistivity electrode.

11. The method according to claim 1 , wherein the forming of the pillar comprises:
preparing a substrate;
etching the substrate to form a line type active region;
patterning the line type active region to form an island type active region;
etching the island type active region to form a bit line trench and a preliminary pillar;
etching the preliminary pillar to form a gate trench which crosses the bit line trench and the pillar, wherein the pillar has first, second, and third side surfaces and the gate trench expose the first side surface; and
forming a first branch trench and a second branch trench which expose the second and third side surfaces of the pillar by extending the gate trench.

12. The method according to claim 11 , wherein the gate electrode comprises a first branch part which is positioned in the first branch trench and a second branch part which is positioned in the second branch trench.

13. A method for fabricating a semiconductor device, comprising:
preparing a substrate which includes a first junction region;
etching the substrate to form a first pillar and a second pillar which are separated from each other in a gate trench;
forming, in a gate trench, a preliminary gate electrode including (i) preliminary first work function liners over lower side surfaces and upper side surfaces of the first and second pillars, and (ii) second work function liners over the upper side surfaces of the first and second pillars;
separating the preliminary gate electrode, and forming a first gate electrode which overlaps with the upper and lower side surfaces of the first pillar and a second gate electrode which overlaps with the upper and lower side of the second pillar;
recessing the preliminary first work function liners to non-overlap with the second work function liners, and forming gaps;
capping the gaps, and forming air gaps; and
forming second junction regions in the first and second pillars to have a depth that overlaps with the air gaps,
wherein each of the first and second pillars has first, second, and third side surfaces and the gate trench expose the first side surface of the first and second pillars.

14. The method according to claim 13 , wherein, before forming of the preliminary gate electrode, the method further comprises:
forming a first branch trench and a second branch trench which expose the second and third side surfaces of the first and second pillars by extending the gate trench.

15. The method according to claim 13 , wherein the preparing of the substrate which includes the first junction region comprises:
preparing the substrate;
etching the substrate, and forming a body and a preliminary first pillar and a preliminary second pillar which are separated from each other by a bit line trench over the body;
forming the first junction region in the body over a bottom surface of the bit line trench; and
forming a bit line which is electrically coupled with the first junction region, in the bit line trench.

16. The method according to claim 15 , wherein the forming of the preliminary first pillar and the preliminary second pillar comprises:
forming a first isolation layer, which defines a line type active region, in the substrate;
cutting the first isolation layer and the line type active region to form an isolation trench and an island type active region;
filling a second isolation layer in the isolation trench; and
etching the island type active region, the first isolation layer, and the second isolation layer to form th

Assignees

• Sk Hynix Inc

Inventors

• Oh Tae-Kyung

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title