Back-to-back stacked integrated circuit assembly

Patent metadata

Field	Value
Publication number	US-9576937-B2
Application number	US-201615130721-A
Country	US
Kind code	B2
Filing date	Apr 15, 2016
Priority date	Dec 21, 2012
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

An integrated circuit assembly includes a first substrate and a second substrate, with active layers formed on the first surfaces of each substrate, and with the second surfaces of each substrate coupled together. A method of fabricating an integrated circuit assembly includes forming active layers on the first surfaces of each of two substrates, and coupling the second surfaces of the substrates together.

First claim

What is claimed is:

1. An integrated circuit assembly comprising:
a first singulated portion of a first wafer having a substrate side and an active layer side; and
a second singulated portion of a second wafer having a substrate side and an active layer side, wherein the first singulated portion and the second singulated portion are coupled substrate side-to-substrate side;
the active layer side of the first singulated portion including a first metal bond pad; and
the active layer side of the second singulated portion including a second metal bond pad, wherein the first singulated portion is thinner than the second singulated portion.

2. The integrated circuit assembly of claim 1 , wherein the integrated circuit assembly does not include a vertical electrical connection through the first singulated portion and the second singulated portion.

3. The integrated circuit assembly of claim 1 , further comprising:
a first printed circuit board electrically coupled to the first metal bond pad by a first solder bump.

4. The integrated circuit assembly of claim 3 , further comprising:
a second printed circuit board electrically coupled to the second metal bond pad by a second solder bump.

5. The integrated circuit assembly of claim 3 , further comprising:
a bond wire electrically coupling the second metal bond pad to the first printed circuit board.

6. The integrated circuit assembly of claim 1 , wherein the first singulated portion comprises a part of a semiconductor-on-insulator wafer.

7. The integrated circuit assembly of claim 6 , wherein the second singulated portion does not comprise a part of a semiconductor-on-insulator wafer.

8. The integrated circuit assembly of claim 1 , wherein the first active layer or the second active layer includes passive devices.

9. An integrated circuit assembly comprising:
a first substrate having a first surface and a second surface,
a first active layer formed on the first surface of the first substrate, the first active layer including a first metal bond pad;
a second substrate having a first surface and a second surface, the second surface of the first substrate being coupled to the second surface of the second substrate, and
a second active layer formed on the first surface of the second substrate, the second active layer including a second metal bond pad, wherein the second substrate is thinner than the first substrate.

10. The integrated circuit assembly of claim 9 , further comprising:
a printed circuit board, the printed circuit board being electrically coupled to the first active layer and the second active layer.

11. The integrated circuit assembly of claim 10 wherein the printed circuit board is electrically coupled to the second active layer through a wire bond.

12. The integrated circuit assembly of claim 9 , wherein the printed circuit board is electrically coupled with a solder bump to the first active layer.

13. The integrated circuit assembly of claim 9 , further comprising an insulating layer interposed between the second surface of the first substrate and the second surface of the second substrate.

14. The integrated circuit assembly of claim 9 , wherein the first substrate comprises a portion of a semiconductor-on-insulator wafer.

15. The integrated circuit assembly of claim 14 , wherein the second substrate does not include a portion of a semiconductor-on-insulator wafer.

16. A back-to-back stacked integrated circuit assembly comprising:
a first singulated portion including a first semiconductor substrate with a first active layer disposed on the first semiconductor substrate;
a second singulated portion including a second semiconductor substrate with a second active layer disposed on the second semiconductor substrate;
a first metal pad on the first active layer;
a second metal pad on the second active layer;
wherein a surface of the first semiconductor substrate opposite the first active layer is coupled to a surface of the second semiconductor substrate opposite the second active layer; and
a printed circuit board electrically coupled with the first metal pad by a solder bump, wherein the first semiconductor substrate is thinner than the second semiconductor substrate.

17. The back-to-back stacked integrated circuit assembly of claim 16 , wherein the back-to-back stacked integrated circuit assembly does not include a vertical electrical connection through the first singulated portion and the second singulated portion.

18. The back-to-back stacked integrated circuit assembly of claim 16 , wherein the first semiconductor substrate comprises a semiconductor-on-insulator substrate.

Assignees

• Qualcomm Inc

Inventors

• Stuber Michael A
• Molin Stuart B

Classifications

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title