Methods for manufacturing a data storage device

Patent metadata

Field	Value
Publication number	US-9576846-B2
Application number	US-201414226770-A
Country	US
Kind code	B2
Filing date	Mar 26, 2014
Priority date	Jul 15, 2013
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches.

First claim

What is claimed is:

1. A method for manufacturing a data storage device, the method comprising:
forming an interlayer dielectric layer on a substrate;
patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches;
forming first bit lines in the first trenches;
after forming the first bit lines, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches; and
forming second bit lines in the second trenches,
wherein bottom surfaces of the second bit lines are formed to be disposed at height that is substantially the same as a height of bottom surfaces of the first bit lines.

2. The method of claim 1 , wherein the first trenches and the second trenches are alternately and repeatedly arranged.

3. The method of claim 1 , wherein top surfaces of the second bit lines are formed to be higher than top surfaces of the first bit lines.

4. The method of claim 1 , wherein the first bit lines and the second bit lines include the same material.

5. The method of claim 1 , further comprising:
etching the interlayer dielectric layer in the peripheral region to form a first interconnection trench; and
forming a first interconnection in the first interconnection trench,
wherein the first interconnection trench is formed substantially simultaneously with the first trenches, and the first interconnection is formed substantially simultaneously with the first bit lines.

6. The method of claim 5 , wherein top surfaces of the second bit lines are formed to be higher than a top surface of the first interconnection.

7. The method of claim 5 , wherein a top surface of the first interconnection has a height that is substantially the same as a height of top surfaces of the first bit lines, and
wherein a bottom surface of the first interconnection has a height that is substantially the same as a height of bottom surfaces of the first bit lines.

8. The method of claim 5 , further comprising:
forming data storage parts arranged two-dimensionally in plan view in a cell region of the substrate, the interlayer dielectric layer covering the data storage parts;
patterning the interlayer dielectric layer in the cell region to form third trenches exposing the data storage parts; and
forming third bit lines in the third trenches,
wherein the third bit lines are formed substantially simultaneously with the first bit lines.

9. The method of claim 8 , wherein a width of each of the third bit lines is smaller than a width of each of the first bit lines and a width of each of the second bit lines.

10. The method of claim 8 , wherein forming the first bit lines, the third bit lines, and the first interconnection comprises:
forming a conductive layer filling the first trenches, the third trenches, and the first interconnection trench; and
planarizing the conductive layer until the interlayer dielectric layer is exposed.

11. The method of claim 5 , further comprising:
etching the interlayer dielectric layer in the peripheral region to form a second interconnection trench; and
forming a second interconnection in the second interconnection trench,
wherein the second interconnection trench is formed substantially simultaneously with the second trenches, and the second interconnection is formed substantially simultaneously with the second bit lines.

12. The method of claim 11 , wherein a top surface of the second interconnection is formed to be higher than a top surface of the first interconnection.

13. The method of claim 11 , wherein a bottom surface of the second interconnection has a height that is substantially the same as a height of a bottom surface of the first interconnection.

14. The method of claim 11 , wherein forming the second trenches and the second interconnection trench comprises:
sequentially forming a first mask layer and a second mask layer on the interlayer dielectric layer, the first bit lines, and the first interconnection;
patterning the second and first mask layers to form openings defining the second trenches and the second interconnection trench;
etching the interlayer dielectric layer using the second and first mask layers having the openings formed therein as etch masks; and
removing the second mask layer.

15. The method of claim 14 , wherein forming the second bit lines and the second interconnection comprises:
forming a conductive layer filling the second trenches and the second interconnection trench;
planarizing the conductive layer until the first mask layer is exposed; and
removing the first mask layer.

16. A method for manufacturing a data storage device, the method comprising:
forming an interlayer dielectric layer on a substrate;
patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches;
forming first bit lines in the first trenches;
after forming the first bit lines, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches;
forming second bit lines in the second trenches;
etching the interlayer dielectric layer in the peripheral region to form a first interconnection trench; and
forming a first interconnection in the first interconnection trench,
wherein the first interconnection trench is formed substantially simultaneously with the first trenches, and the first interconnection is formed substantially simultaneously with the first bit lines.

17. The method of claim 16 , wherein top surfaces of the second bit lines are formed to be higher than a top surface of the first interconnection.

18. The method of claim 16 , wherein a top surface of the first interconnection has a height that is substantially the same as a height of top surfaces of the first bit lines, and
wherein a bottom surface of the first interconnection has a height that is substantially the same as a height of bottom surfaces of the first bit lines.

19. A method for manufacturing a data storage device, the method comprising:
forming an interlayer dielectric layer on a substrate;
forming first trenches in the interlayer dielectric layer in a cell region of the substrate;
forming second trenches in the interlayer dielectric layer in a peripheral region of the substrate;
forming first bit lines in the first trenches using a first damascene process; and
forming second bit lines in the second trenches using a second damascene process that is separate from the first damascene process,
wherein bottom surfaces of the second bit lines are formed to be disposed at height that is lower than a height of bottom surfaces of the first bit lines, and
wherein top surfaces of the second bit lines are formed to be higher than top surfaces of the first bit lines.

20. The method of claim 19 , further comprising:
forming third trenches in the interlayer dielectric layer between the second bit lines in the peripheral region; and
forming third bit lines in the third trenches.

Assignees

• Lee Kilho
• Samsung Electronics Co Ltd

Inventors

• Lee Kilho

Classifications

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title

• H01L27/228

  Electricity · mapped topic

• H01L21/76816 Primary

  Electricity · mapped topic