Sensing multiple reference levels in non-volatile storage elements

US9576673B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9576673-B2
Application numberUS-201414508615-A
CountryUS
Kind codeB2
Filing dateOct 7, 2014
Priority dateOct 7, 2014
Publication dateFeb 21, 2017
Grant dateFeb 21, 2017

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  5. First independent claim

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Abstract

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Disclosed herein are techniques for sensing multiple reference levels in non-volatile storage elements without changing the voltage on the selected word line. One aspect includes determining a first condition of a selected non-volatile storage element with respect to a first reference level based on whether a sensing transistor conducts in response to a sense voltage on a sense node. Then, a voltage on the source terminal of the sensing transistor is modified after determining the first condition with respect to the first reference level. A second condition of the selected non-volatile storage element is then determined with respect to a second reference level based on whether the sensing transistor conducts in response to the sense voltage on the sense node. This allows two different reference levels to be efficiently sensed. Dynamic power is saved due low capacitance of the sensing transistor relative to the sense node.

First claim

Opening claim text (preview).

We claim: 1. A non-volatile storage device, comprising: a selected non-volatile storage element; a charge storage device coupled to the selected non-volatile storage element and a sensing device having a control terminal coupled to the charge storage device, a pre-charge circuit and bit line connection circuit configured to develop a sense voltage on the charge storage device in response to a signal from a state machine, the sense voltage is developed based on connecting the selected non-volatile storage element to the charge storage device for a sense time; a processor configured to determine whether the sensing device activates in response to the sense voltage that was developed on the charge storage device based on connecting the selected non-volatile storage element to the charge storage device for the sense time; the processor further configured to determine a first condition of the selected non-volatile storage element with respect to a first reference level based on whether the sensing device activates in response to the sense voltage developed on the charge storage device, a voltage supply configured to modify a voltage on a second terminal of the sensing device other than the control terminal after determining the first condition in response to a signal from the state machine; the processor configured to determine whether the sensing device activates after modifying the voltage on the second terminal in response to the sense voltage that was developed on the charge storage device based on connecting the selected non-volatile storage element to the charge storage device for the sense time, the processor configured to determine a second condition of the selected non-volatile storage element with respect to a second reference level based on whether the sensing device activates in response to the sense voltage developed on the charge storage device after modifying the voltage on the second terminal of the sensing device. 2. The non-volatile storage device of claim 1 , wherein the bit line connection circuit is configured to connect the charge storage device to a bit line for the sense time to allow a current from the bit line to discharge the charge storage device for the sense time. 3. The non-volatile storage device of claim 1 , wherein the voltage supply increases a voltage on the second terminal in response to a signal from the state machine in order to modify the voltage on the second terminal. 4. The non-volatile storage device of claim 1 , wherein the pre-charge circuit is configured to modify a voltage on the charge storage device after the first condition of the selected non-volatile storage element is determined with respect to the first reference level, the processor is configured to determine whether the sensing device activates in response to the modified voltage on the charge storage device, the processor is configured to determine a third condition of the selected non-volatile storage element with respect to a third reference level based on whether the sensing device activates in response to the modified voltage on the charge storage device, the voltage supply is configured to modify the voltage on the second terminal of the sensing device after it is determined whether the sensing device activates in response to the modified voltage on the charge storage device, the third reference level being between the first reference level and the second reference level. 5. The non-volatile storage device of claim 1 , further comprising a data latch that stores a first result in response to whether the sensing device activates in response to the sense voltage on the charge storage device prior to modifying the voltage on the second terminal of the sensing device, the first result indicates whether the selected non-volatile storage element has a threshold voltage above or below a first target threshold voltage, the data latch stores a second result in response to whether the sensing device activates in response to the sense voltage on the charge storage device after modifying the voltage on the second terminal of the sensing device, the second result indicates whether the selected non-volatile storage element has a threshold voltage above or below a second target threshold voltage. 6. The non-volatile storage device of claim 1 , wherein when the pre-charge circuit and bit line connection circuit develop the sense voltage on the charge storage device the voltage supply applies a voltage to a word line associated with the selected non-volatile storage element in response to a signal from the state machine. 7. The non-volatile storage device of claim 1 , wherein the selected non-volatile storage element is part of a 3D memory array. 8. The non-volatile storage device of claim 1 , wherein the selected non-volatile storage element comprises a charge trapping region that store data. 9. The non-volatile storage device of claim 1 , wherein the sensing device comprises a transistor having a source terminal, wherein the second terminal is the source terminal. 10. A method comprising: developing a sense voltage on a sense node connected to a sensing device, including connecting the sense node to a selected non-volatile storage element to discharge the sense node for a sense time; determining a first condition of the selected non-volatile storage element with respect to a first reference level based on whether the sensing device activates in response to the sense voltage that was developed on the sense node based on discharging the sense node for the sense time; modifying a voltage on a node of the sensing device after determining the first condition with respect to the first reference level; and determining a second condition of the selected non-volatile storage element with respect to a second reference level based on whether the sensing device activates after modifying the voltage on the node of the sensing device in response to the sense voltage that was developed on the sense node based on discharging the sense node for the sense time. 11. The method of claim 10 , wherein the modifying a voltage on the node of the sensing device comprises: increasing a voltage on the sense node of the sensing device. 12. The method of claim 10 , wherein the developing a sense voltage on a sense node comprises: charging the sense node; connecting the sense node to a bit line that is associated with the selected non-volatile storage element; and allowing a current from the bit line to discharge the sense node for the sense time. 13. The method of claim 10 , further comprising: modifying a voltage on the sense node after determining the first condition of the selected non-volatile storage element with respect to the first reference level; determining whether the sensing device activates in response to the modified voltage on the sense node prior to modifying the voltage on the node of the sensing device; and determining a third condition of the selected non-volatile storage element with respect to a third reference level based on whether the sensing device activates in response to the modified voltage on the sense node prior to modifying the voltage on the node of the sensing device, wherein the modifying a voltage on a node of the sensing device is performed after determining whether the sensing device activates in response to the modified voltage on the sense node, the third reference level being between the first reference level and the second reference level. 14. The method of claim 10 , wherein the first reference level is whether the selected non-volatile storage element has a threshold voltage above or below a first threshold voltage, whe

Assignees

Inventors

Classifications

  • G11C16/28Primary

    using differential sensing or reference cells, e.g. dummy cells · CPC title

  • Multilevel programming verification · CPC title

  • Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

  • Sensing or reading circuits; Data output circuits · CPC title

  • comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

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What does patent US9576673B2 cover?
Disclosed herein are techniques for sensing multiple reference levels in non-volatile storage elements without changing the voltage on the selected word line. One aspect includes determining a first condition of a selected non-volatile storage element with respect to a first reference level based on whether a sensing transistor conducts in response to a sense voltage on a sense node. Then, a vo…
Who is the assignee on this patent?
Sandisk 3D Llc, Sandisk Technologies Llc
What technology area does this patent fall under?
Primary CPC classification G11C16/28. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 21 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).