Supporting atomic accumulation with an addressable accumulator

Patent metadata

Field	Value
Publication number	US-9575890-B2
Application number	US-201414191566-A
Country	US
Kind code	B2
Filing date	Feb 27, 2014
Priority date	Feb 27, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

Atomically accumulating memory updates in a computer system configured with an accumulator that is memory mapped. The accumulator includes an accumulator memory and an accumulator queue and is configured to communicatively couple to a processor. Included is receiving from the processor, by the accumulator, an accumulation request. The accumulation request includes an accumulation operation identifier and data. Based on determining, by the accumulator, that the accumulator can immediately process the request, immediately processing the request. Processing the request includes atomically updating a value in the accumulator memory, by the accumulator, based on the operation identifier and data of the accumulation request. Based on determining, by the accumulator, that the accumulator is actively processing another accumulation request, queuing, by the accumulator, the accumulation request for later processing. Further included is signaling the processor, by the accumulator, the completion of the accumulation request.

First claim

What is claimed is:

1. A computer program product for atomically accumulating memory updates in a computer system configured with an accumulator that is memory mapped, the accumulator mapped to a memory address, having an accumulator memory and an accumulator queue, the accumulator configured to communicatively couple to a processor, the computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
receiving from the processor, by the accumulator, an accumulator request directed to, the memory address, the accumulator request comprising an accumulator operation identifier and data; and
based on determining, by the accumulator, that the accumulator is available to immediately process the request:
immediately processing the request, the processing comprising atomically updating a value in the accumulator memory, by the accumulator, based on the operation identifier and data in the accumulator request; and
notifying the processor, by the accumulator, of a completion of the accumulator request;

based on determining, by the accumulator, that the accumulator is not available to immediately process the request, due to the accumulator actively processing another accumulator request, queuing, by the accumulator, the accumulator request, the queued request to be processed when the accumulator becomes available.

2. The computer program product according to claim 1 , further comprising:
based on the accumulator operation identifier being a store-initial-value operation, storing an initial value into the accumulator memory; and
based on the accumulator operation identifier being a retrieve-value operation, performing a) and b) comprising:
a) retrieving the value from the accumulator memory; and
b) storing the value to a non-accumulator location.

3. The computer program product according to claim 1 , further comprising:
based on the value resulting from processing the request reaching a threshold value, signaling the processor, by the accumulator, the value threshold being reached.

4. The computer program product according to claim 1 , further comprising:
based on reaching a queue length threshold after queuing the accumulator request, signaling the processor, by the accumulator, the queue length threshold being reached.

5. The computer program product according to claim 1 , wherein the accumulator is mapped to a plurality of memory addresses having corresponding accumulator memories and corresponding accumulator queues.

6. The computer program product according to claim 5 , further comprising:
determining, by the accumulator upon receiving the accumulator request, a memory address of the plurality of memory addresses to be used for processing the request.

7. A computer system for atomically accumulating memory updates in a computer system configured with an accumulator that is memory mapped, the computer system comprising:
an accumulator mapped to a memory address, having an accumulator memory and an accumulator queue, the accumulator configured to communicatively couple to a processor wherein the accumulator is configured to perform a method, said method comprising:
receiving from the processor, by the accumulator, an accumulator request directed to the memory address, the accumulator request comprising an accumulator operation identifier and data; and
based on determining, by the accumulator, that the accumulator is available to immediately process the request:
immediately processing the request, the processing comprising atomically updating a value in the accumulator memory, by the accumulator, based on the operation identifier and data in the accumulator request; and
notifying the processor, by the accumulator, of a completion of the accumulator request;

based on determining, by the accumulator, that the accumulator is not available to immediately process the request, due to the accumulator actively processing another accumulator request, queuing, by the accumulator, the accumulator request, the queued request to be processed when the accumulator becomes available.

8. The computer system according to claim 7 , further comprising:
based on the accumulator operation identifier being a store-initial-value operation, storing an initial value into the accumulator memory; and
based on the accumulator operation identifier being a retrieve-value operation, performing a) and b) comprising:
a) retrieving the value from the accumulator memory; and
b) storing the value to a non-accumulator location.

9. The computer system according to claim 7 , further comprising:
based on the value resulting from processing the request reaching a threshold value, signaling the processor, by the accumulator, the value threshold being reached.

10. The computer system according to claim 7 , further comprising:
based on reaching a queue length threshold after queuing the accumulator request, signaling the processor, by the accumulator, the queue length threshold being reached.

11. The computer system according to claim 7 , wherein the accumulator is emulated by the processor, the processor comprising:
local memory or registers allocated for an emulated memory address of an accumulator, an emulated accumulator value, and an emulated accumulator instruction queue; and
an accumulator arithmetic logic unit, the arithmetic logic unit comprising an adder.

12. The computer system according to claim 11 , the processor further comprising:
an emulated threshold value, the arithmetic logic unit comparing the emulated threshold value with the emulated accumulator value to determine if the value threshold is reached.

13. The computer system according to claim 11 , further comprising:
the processor emulating a plurality of accumulators, the plurality of emulated memory addresses of the plurality of accumulators initialized based on a plurality of program specified memory addresses, each of the plurality of emulated memory addresses for controlling one of the plurality of emulated accumulator values.

14. The computer system according to claim 13 , wherein the processor emulates the plurality of arithmetic logic units with a single arithmetic logic unit.

15. The computer system according to claim 7 , wherein the accumulator is mapped to a plurality of memory addresses having corresponding accumulator memories and corresponding accumulator queues.

16. The computer system according to claim 15 , further comprising:
determining, by the accumulator upon receiving the accumulator request, a memory address of the plurality of memory addresses to be used for processing the request.

Assignees

• IBM

Inventors

• Busaba Fadi Y
• Gschwind Michael Karl
• Schwarz Eric M

Classifications

• G06F9/467 Primary

  Transactional memory (G06F9/528 takes precedence) · CPC title

• G06F9/528

  by using speculative mechanisms · CPC title

• G06F12/0284 Primary

  Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163) · CPC title

• G06F2212/314

  In storage network, e.g. network attached cache · CPC title

• G06F12/084

  with a shared cache · CPC title