Non-volatile memory interface

Patent metadata

Field	Value
Publication number	US-9575882-B2
Application number	US-201514866385-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 28, 2010
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

Apparatuses, systems, methods, and computer program products are disclosed for a memory controller. An apparatus includes a volatile memory medium located on a memory module. An apparatus includes a non-volatile memory medium located on a memory module. A memory controller is located on a memory module. A memory controller may be configured to provide access to at least a non-volatile memory medium over a direct wire interface with a processor.

First claim

What is claimed is:

1. An apparatus comprising:
a volatile memory medium located on a memory module;
a non-volatile memory medium located on the memory module; and
a memory controller located on the memory module, the memory controller configured to provide access to at least the non-volatile memory medium over a direct wire interface with a processor by way of a command protocol, the interface comprising a control path for the command protocol, the control path enabling the memory controller to distinguish among different memory modules, the command protocol configured to support one or more commands that are not supported by a standard volatile memory interface.

2. The apparatus of claim 1 , wherein the one or more commands comprise one or more synchronous commands and the memory controller is configured to execute the one or more commands asynchronously in response to receiving the one or more commands.

3. The apparatus of claim 1 , wherein the memory controller is configured to receive a signal from the processor, using the command protocol, that the one or more commands will not be executed in response to the processor determining that the memory controller is not capable of satisfying the one or more commands.

4. The apparatus of claim 1 , wherein the memory controller is configured to communicate with the volatile memory medium by way of a second protocol, the command protocol and the second protocol comprising different protocols.

5. The apparatus of claim 4 , wherein the memory module is configured to notify the memory controller of one or more memory attributes of the non-volatile memory medium, the memory controller configured to direct data to one of the non-volatile memory medium, the volatile memory medium, a memory division on the non-volatile memory medium, and a memory division on the volatile memory medium based on the one or more memory attributes.

6. The apparatus of claim 1 , further comprising a second memory controller configured to communicate with the volatile memory medium by way of a second protocol, the command protocol and the second protocol comprising different protocols.

7. The apparatus of claim 6 , wherein the second memory controller is coupled to the processor.

8. The apparatus of claim 1 , wherein the memory controller is configured to associate sequence indicators with data on the non-volatile memory medium, wherein the sequence indicators determine an ordered sequence of memory operations performed on the non-volatile memory medium.

9. The apparatus of claim 1 , wherein the memory controller is configured to associate checkpoint information with data on the non-volatile memory medium, wherein the checkpoint information is organized in an ordered sequence of memory checkpoint operations performed on the non-volatile memory medium.

10. The apparatus of claim 1 , wherein the memory controller is configured to:
store data in a format that associates the data with respective logical memory addresses on the non-volatile memory medium;
maintain an index of associations between logical memory addresses of the data and physical storage memory locations comprising the data on the non-volatile memory medium; and
reconstruct the index using the logical memory addresses and sequence indicators associated with the data on the non-volatile memory medium, wherein reconstructing the index comprises replaying a sequence of changes made to the index using the logical memory addresses and the sequence indicators associated with the data on the non-volatile memory medium.

11. The apparatus of claim 10 , wherein reconstructing the index comprises rolling back a sequence of changes made to the index from a last change back to a valid checkpoint indicator using the logical memory addresses and the sequence indicators associated with the data on the non-volatile memory medium.

12. The apparatus of claim 1 , wherein the one or more commands comprise one or more of a query command, a directive command, and a hint command.

13. The apparatus of claim 1 , wherein the memory controller is configured to operate one or more memory maintenance functions on the non-volatile memory medium to optimize non-volatile memory performance one of independent of the processor and in response to receiving one or more memory management commands from the processor using the command protocol.

14. An apparatus comprising:
means for volatile data storage on a memory module;
means for non-volatile data storage on the memory module; and
means for providing access to at least the non-volatile data storage over a direct wire interface with a processor by way of a command protocol, the interface comprising a control path for the command protocol, the control path enabling distinguishing among different memory modules, the command protocol configured to support one or more commands that are not supported by a standard volatile memory interface.

15. The apparatus of claim 14 , further comprising means for communicating with the means for volatile data storage by way of a second protocol, the command protocol and the second protocol comprising different protocols.

16. The apparatus of claim 15 , further comprising:
means for notifying of one or more memory attributes of the means for non-volatile data storage; and
means for directing data to locations on one of the means for non-volatile data storage and the means for volatile data storage based on the one or more memory attributes.

17. The apparatus of claim 14 , further comprising means for associating checkpoint information with data on the non-volatile data storage, wherein the checkpoint information is organized in an ordered sequence of memory checkpoint operations performed on the means for non-volatile data storage.

18. The apparatus of claim 14 , further comprising:
means for storing data in a format that associates the data with respective logical memory addresses on the means for non-volatile data storage;
means for maintaining an index of associations between logical memory addresses of the data and physical storage locations comprising the data on the means for non-volatile data storage; and
means for reconstructing the index using the logical memory addresses and sequence indicators associated with the data on the means for non-volatile data storage by replaying a sequence of changes made to the index using the logical memory addresses and the sequence indicators associated with the data on the means for non-volatile data storage.

19. The apparatus of claim 18 , further comprising means for associating sequence indicators with the data on the means for non-volatile data storage, wherein the sequence indicators determine an ordered sequence of memory operations performed on the means for non-volatile data storage.

20. A system comprising:
a memory controller of a processor, the memory controller configured to send one or more commands of a command protocol over a direct wire interface; and
a non-volatile memory controller configured to provide access to at least a non-volatile memory medium over the direct wire interface with the processor by way of the command protocol, the interface comprising a control path for the command protocol, the control path enabling the memory controller to distinguish among different memory modules, the command protocol configured to support one or more commands that are not supported by a standard volatile memory interface.

Assignees

• Longitude Entpr Flash S A R L
• Sandisk Technologies Llc

Inventors

• Nellans David
• Wipfel Robert

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0238 Primary

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F2212/202

  Non-volatile memory · CPC title

• G06F13/426

  using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic