Push instruction for pushing a message payload from a sending thread to a receiving thread

Patent metadata

Field	Value
Publication number	US-9575825-B2
Application number	US-201414581144-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A processor core of a data processing system receives a push instruction of a sending thread that requests that a message payload identified by at least one operand of the push instruction be pushed to a mailbox of a receiving thread. In response to receiving the push instruction, the processor core executes the push instruction of the sending thread. In response to executing the push instruction, the processor core initiates transmission of the message payload to the mailbox of the receiving thread. In one embodiment, the processor core initiates transmission of the message payload by transmitting a co-processor request to a switch of the data processing system via an interconnect fabric.

First claim

What is claimed is:

1. A processing unit for a data processing system, the processing unit comprising:
a memory; and
a processor core coupled to the memory, wherein the processor core includes at least one execution unit that, responsive to receiving a push instruction of a sending thread that requests that a message payload identified by at least one operand of the push instruction be pushed to a mailbox of a receiving thread and that includes a completion enable parameter that is enabled, executes the push instruction, and wherein the processing unit, responsive to execution, by the processor core, of the push instruction including the enabled completion enable parameter, initiates transmission of the message payload to the mailbox of the receiving thread by:
accessing the message payload; and
transmitting, to a switch in the data processing system via an interconnect fabric of the data processing system, a co-processor request that requests the switch to push the payload to the mailbox of the receiving thread, wherein the co-processor request includes at least the message payload, a parameter from which switch can identify the mailbox of the receiving thread, and a completion enable parameter requesting notification of the sending thread of injection of the message payload into the mailbox of the receiving thread.

2. The processing unit of claim 1 , wherein:
the push instruction includes a co-processor type parameter;
the data processing system includes multiple switches including the switch; and
the processor core transmits the co-processor type parameter in the co-processor request on the interconnect fabric to identify the switch as responsible for servicing the co-processor request.

3. The processing unit of claim 1 , wherein:
the switch includes a data structure including a plurality of entries;
the push instruction includes a logical window parameter identifying a particular entry among the plurality of entries in the data structure; and
the parameter in the co-processor request from which the switch can identify the mailbox is the logical window parameter.

4. The processing unit of claim 1 , wherein:
the push instruction is a first push instruction;
the sending thread includes a second push instruction following the first push instruction in program order; and
the processor core executes the first push instruction and thereafter executes the second push instruction only in response to receipt of an indication that the switch claimed the co-processor request.

5. The processing unit of claim 1 , wherein:
the push instruction includes a report enable parameter that is enabled; and
the processing unit, responsive to the report enable parameter being enabled in the push instruction, includes in the co-processor request a report enable parameter requesting notification of the receiving thread of injection of the message payload into the mailbox of the receiving thread.

6. A data processing system, comprising:
a memory;
an interconnect fabric;
a processing unit coupled to the memory and to the interconnect fabric, wherein the processing unit includes a processor core including at least one execution unit that, responsive to receiving a push instruction of a sending thread that requests that a message payload identified by at least one operand of the push instruction be pushed to a mailbox of a receiving thread and that includes a completion enable parameter that is enabled, executes the push instruction, and wherein the processing unit, responsive to execution, by the processor core, of the push instruction including the enabled completion enable parameter, initiates transmission of the message payload to the mailbox of the receiving thread by:
accessing the message payload;
transmitting, via the interconnect fabric, a co-processor request that requests the switch to push the payload to the mailbox of the receiving thread, wherein the co-processor request includes at least the message payload a parameter from which switch can identify the mailbox of the receiving thread, and a completion enable parameter requesting notification of the sending thread of injection of the message payload into the mailbox of the receiving thread; and

a switch coupled to the interconnect fabric, wherein the switch, responsive to the co-processor request, injects the message payload into the mailbox of the receiving thread utilizing the parameter.

7. The data processing unit of claim 6 , wherein:
the push instruction includes a co-processor type parameter;
the data processing system includes multiple switches including the switch; and
the processor core transmits the co-processor type parameter in the co-processor request on the interconnect fabric to identify the switch as responsible for servicing the co-processor request.

8. The data processing unit of claim 6 , wherein:
the switch includes a data structure including a plurality of entries;
the push instruction includes a logical window parameter identifying a particular entry among the plurality of entries in the data structure; and
the parameter in the co-processor request from which the switch can identify the mailbox is the logical window parameter.

9. The data processing unit of claim 6 , wherein:
the push instruction is a first push instruction;
the sending thread includes a second push instruction following the first push instruction in program order; and
the processor core executes the first push instruction and thereafter executes the second push instruction only in response to receipt of an indication that the switch claimed the co-processor request.

10. The data processing unit of claim 6 , wherein:
the push instruction includes a report enable parameter that is enabled; and
the processing unit, responsive to the report enable parameter being enabled in the push instruction, includes in the co-processor request a report enable parameter requesting notification of the receiving thread of injection of the message payload into the mailbox of the receiving thread.

Assignees

• IBM

Inventors

• Arimilli Lakshminarayana B
• Drerup Bernard C
• Frey Bradly G
• Guthrie Guy L
• Irish John D
• Starke William J
• Stuecheli Jeffrey A

Classifications

• G06F9/546 Primary

  Message passing systems or structures, e.g. queues · CPC title

• G06F15/167

  using a common memory, e.g. mailbox · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title