Monitoring accesses of a thread to multiple memory controllers and selecting a thread processor for the thread based on the monitoring

Patent metadata

Field	Value
Publication number	US-9575806-B2
Application number	US-201213538971-A
Country	US
Kind code	B2
Filing date	Jun 29, 2012
Priority date	Jun 29, 2012
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A method of an aspect includes running a plurality of threads on a plurality of thread processors. Memory accesses, of a thread of the plurality that is running on a first thread processor of the plurality, are monitored to both a first memory through a first memory controller and a second memory through a second memory controller. A second thread processor of the plurality is selected for a thread based on the monitoring of the memory accesses of the thread to both the first memory and the second memory. Installation of the thread, for which the second thread processor was selected, is initiated on the second thread processor. Other methods, apparatus, and systems are also disclosed.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of thread processors of a multi-core processor to run a plurality of threads;
a first memory controller directly coupled to a first thread processor and indirectly coupled to at least a second thread processor via a first set of one or more intervening thread processors, the first memory controller to provide access to a first memory;
a second memory controller directly coupled to a third thread processor and indirectly coupled to at least a fourth thread processor via one or more intervening thread processors to provide access to a second memory;
a memory controller access monitor unit coupled with the second thread processor of the plurality of thread processors, the memory controller access monitor unit to monitor proportions of memory accesses, of a thread of the plurality of threads that is to run on the second thread processor, to both the first memory and the second memory, wherein the thread is to access the first memory via the first set of the one or more intervening thread processors and the first memory controller, wherein the thread is to access the second memory via at least the third thread processor and the second memory controller; and
a thread processor selector unit coupled with the memory controller access monitor unit, the thread processor selector unit to select a destination thread processor of the plurality of thread processors of the multi-core processor based on the monitored proportions of memory accesses by the thread to both the first memory and the second memory and at least a queueing delay associated with accessing the first memory, wherein the queueing delay is to incorporate one or more queueing delays for hops through the first set of the one or more intervening thread processors and is to incorporate a queueing delay within the first memory controller; and
a thread migration initiation unit coupled with the memory controller access monitor unit, the thread migration initiation unit to initiate migration of the thread to the destination thread processor of the plurality of thread processors of the multi-core processor.

2. The apparatus of claim 1 , wherein the thread processor selector unit is to select the destination thread processor to improve overall memory access latency from the thread to the first and second memories.

3. The apparatus of claim 1 , further comprising a memory controller access intensity determination unit coupled with the memory controller access monitor unit, the memory controller access intensity determination unit to determine that the thread, for which the memory controller access monitor unit is to monitor the accesses to both the first and second memory, is a memory access intensive thread.

4. The apparatus of claim 1 , wherein the memory controller access monitor unit is to monitor at least one of: (a) a proportion of instructions processed by the thread that are cache misses; and (b) a count of cycle stalls for the thread.

5. The apparatus of claim 1 , wherein the second thread processor is coupled with the first memory controller through a plurality of intervening thread processors coupled between the second thread processor and the first memory controller.

6. The apparatus of claim 1 , wherein the fourth thread processor is coupled with the second memory controller through a plurality of intervening thread processors.

7. The apparatus of claim 1 , further comprising a thread installation unit to install the thread on the destination thread processor, wherein the thread installation unit comprises logic of an integrated circuit having the second thread processor.

8. A system comprising:
a first memory;
a second memory;
a plurality of thread processors of a multi-core processor to run a plurality of threads;
a first memory controller, directly coupled to the first memory, and directly coupled to a first thread processor, and indirectly coupled to at least a second thread processor via a first set of one or more intervening thread processors, the first memory controller to provide access to the first memory;
a second memory controller, directly coupled to the second memory, directly coupled to a third thread processor, and indirectly coupled to at least a fourth thread processor via one or more intervening thread processors, to provide access to the second memory;
a memory controller access monitor unit coupled with the second thread processor of the plurality of thread processors, the memory controller access monitor unit to monitor proportions of memory accesses, of a thread of the plurality of threads that is to run on the second thread processor, to both the first memory and the second memory, wherein the thread is to access the first memory via the first set of the one or more intervening thread processors and the first memory controller, wherein the thread is to access the second memory via at least the third thread processor and the second memory controller; and
a thread processor selector unit coupled with the memory controller access monitor unit, the thread processor selector unit to select a destination thread processor of the plurality of thread processors of the multi-core processor based on the monitored proportions of memory accesses by the thread to both the first memory and the second memory and at least a queueing delay associated with accessing the first memory, wherein the queueing delay is to incorporate one or more queueing delays for hops through the first set of the one or more intervening thread processors and is to incorporate a queueing delay within the first memory controller; and
a thread migration initiation unit coupled with the memory controller access monitor unit, the thread migration initiation unit to initiate migration of the thread to the destination thread processor of the plurality of thread processors of the multi-core processor.

9. The system of claim 8 , wherein the thread processor selector unit is to select the destination thread processor to improve overall memory access latency from the thread to the first and second memories.

10. The system of claim 8 , further comprising a memory controller access intensity determination unit coupled with the memory controller access monitor unit, the memory controller access intensity determination unit to determine that the thread, for which the memory controller access monitor unit is to monitor the accesses to both the first and second memory, is a memory access intensive thread.

11. The system of claim 8 , wherein the memory controller access monitor unit is to monitor at least one of: (a) a proportion of instructions processed by the thread that are cache misses; and (b) a count of cycle stalls for the thread.

12. The system of claim 8 , wherein the second thread processor is coupled with the first memory controller through a plurality of intervening thread processors coupled between the second thread processor and the first memory controller.

13. The system of claim 8 , wherein the fourth thread processor is coupled with the second memory controller through a plurality of intervening thread processors.

14. The system of claim 8 , further comprising a thread installation unit to install the thread on the destination thread processor, wherein the thread installation unit comprises logic of an integrated circuit having the second thread processor.

15. A method comprising:
running a plurality of threads on a plurality of thread processors of a multi-core processor on a single integrated circuit substrate, wherein at least a first thread processor of the plurality of thread processors is directly coupled to a fi

Assignees

• Wang Ren
• Ma Ling
• Samih Ahmad
• Bian Zhaojuan
• Intel Corp

Inventors

• Wang Ren
• Ma Ling
• Samih Ahmad
• Bian Zhaojuan

Classifications

• G06F9/5027 Primary

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F2209/502

  Proximity · CPC title

• G06F2209/501

  Performance criteria · CPC title

• Y02B60/142

  Cross-Sectional Technologies · mapped topic

• G06F13/4068

  Electrical coupling · CPC title