Memory system and electronic device including memory system

Patent metadata

Field	Value
Publication number	US-9575759-B2
Application number	US-201514624596-A
Country	US
Kind code	B2
Filing date	Feb 18, 2015
Priority date	Apr 8, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A memory system processing data according to a received first request may include a main memory and a memory controller. The main memory may comprise a first area and a second area, and may be configured to provide data from the first area to the second area. The memory controller may comprise a scoreboard configured to indicate that a first piece of sub-data of a first set of sub-data of the data has been provided from the first area to the second area. Based on the scoreboard, the memory controller may be configured to perform processing of the first request by using the first piece of sub-data before providing of other pieces of sub-data of the first set of sub-data from the first area to the second area is completed.

First claim

What is claimed is:

1. A memory system processing data according to a received first request, the memory system comprising:
a first memory comprising a first area and a second area, and configured to provide data from the first area to the second area; and
a memory controller comprising a scoreboard configured to indicate that a first piece of sub-data of a first set of sub-data of the data has been provided from the first area to the second area,
wherein, based on the scoreboard, the memory controller is configured to perform processing of the first request by using the first piece of sub-data before providing of other pieces of sub-data of the first set of sub-data from the first area to the second area is completed, and
wherein the scoreboard is configured to:
store an in-use bit indicating whether provision of the first set of sub-data of the data to the second area is being performed,
store a tag indicating a start address of the second area, and
store a plurality of full/empty bits respectively indicating whether each piece of sub-data of the first set of sub-data has been provided to a respective sub-area of the first set of sub-areas of the second area.

2. The memory system of claim 1 , wherein the first memory comprises a three-dimensional memory array.

3. The memory system of claim 1 , wherein the scoreboard comprises a first register set comprising a first register configured to store the in-use bit, a second register configured to store the tag, and a plurality of third registers each configured to store each of the plurality of full/empty bits corresponding to the first set of sub-areas of the second area.

4. The memory system of claim 3 , wherein the first request is processed in units of macro operations, the second area is set to have a size corresponding to the units of macro operations, and the plurality of third registers are provided in a number corresponding to the units of macro operations.

5. The memory system of claim 4 , wherein the memory controller differently sets a size of each of the plurality of sub-areas indicated by one of the plurality of third registers according to a size of the data required for processing the first request.

6. The memory system of claim 3 , wherein the memory controller comprises at least a second additional register set indicating whether provision of a second set of sub-data of the data has been provided to a second set of sub-areas of the second area,
wherein the plurality of third registers of the first register set comprises m registers each having k data bits, and a plurality of third registers of the second register set comprises n registers each having l data bits, m is equal to or different from n and k is equal to or different from l, and
wherein the memory controller is configured to assign one of the first register set and the second register set based on a size of the data required for processing the first request.

7. The memory system of claim 1 , wherein, when an i-th sub-data and an (i+1)th sub-data of the first set of sub-data are sequentially transmitted to the second area, and one of the plurality of full/empty bits indicates that the i-th sub-data is the last sub-data transmitted to the second area, the memory controller is configured to process the first request on the first set of sub-data up to the i-th sub-data and then interlock-process the first request on the (i+1)th sub-data.

8. The memory system of claim 1 , wherein a result of the processing of the first request by using the first set of sub-data provided to the second area has been provided to a third area of the first memory, and the memory controller is configured to process a second request by using data provided to the third area, before an operation performed based on the first request is completed.

9. A memory system processing data according to a received first request, the memory system comprising:
a first memory comprising a first area and a second area, and configured to provide data from the first area to the second area; and
a memory controller comprising a scoreboard configured to indicate that a first piece of sub-data of a first set of sub-data of the data has been provided from the first area to the second area,
wherein, based on the scoreboard, the memory controller is configured to perform processing of the first request by using the first piece of sub-data before providing of other pieces of sub-data of the first set of sub-data from the first area to the second area is completed, and
wherein the memory controller comprises:
a control circuit configured to generate a first control signal indicating a control operation to process the first request;
a scoreboard checking circuit configured to generate a second control signal based on a result of checking the scoreboard in response to the first control signal;
a performing circuit configured to perform transmission of the data from the first area to the second area in a unit of a piece of sub-data, perform the first request by using the sub-data transmitted to the second area in response to the second control signal, and generate a third control signal; and
a scoreboard updating circuit configured to update the scoreboard in response to the third control signal and generate a fourth control signal based on a result of the updating.

10. The memory system of claim 9 , wherein the first request is for all pieces of sub-data of the first set of sub-data, the memory controller further comprises a mode setting circuit that is configured to control the control circuit, the scoreboard checking circuit, the performing circuit, and the scoreboard updating circuit so that the first request is performed after the all of pieces of sub-data of the first set of sub-data are all transmitted from the first area to the second area, in response to a mode signal.

11. The memory system of claim 1 , wherein the first request is received from a first device that is located outside the memory system and the first device is configured to execute an application related to the first request.

12. The memory system of claim 1 , further comprising a second memory that is configured to transmit data corresponding to the first request to the first memory or store data processed corresponding to the first request.

13. A semiconductor device comprising:
a first register set including a first set of registers configured to:
indicate whether a first operation is being performed on a second area of a memory including a first area and the second area; and
indicate whether the first operation is completed on a first sub-area of a first set of sub-areas of the second area; and

a second register set including a second set of registers configured to:
indicate whether the first operation is being performed on a second set of sub-areas of the second area; and
indicate whether the first operation is completed on a first sub-area of the second set of sub-areas,

wherein the semiconductor device is configured to, while the first operation is being performed on the other sub-areas of the second area, perform a second operation on the second area by using data resulting from the first operation on the first sub-area, and
wherein the semiconductor device is configured so that the memory performs the second operation on the first sub-area of the second set of sub-areas when the second register set indicates that the first operation is completed on the first sub-area of the second set of sub-areas.

14. The semiconductor device of claim 13 , wherein the first operation includes copying data from the first area to the second area of the memory, or loading data after a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Sang-Yeun

Classifications

• G06F12/0638 Primary

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G11C2207/2236

  Copy · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G06F9/30141 Primary

  Implementation provisions of register files, e.g. ports · CPC title