Cache control device having fault-tolerant function and method of operating the same

Patent metadata

Field	Value
Publication number	US-9575692-B2
Application number	US-201514690843-A
Country	US
Kind code	B2
Filing date	Apr 20, 2015
Priority date	Apr 23, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

The cache control device having the fault-tolerant function includes a cache memory configured to store first data with respect to a specific address read from a main memory, and generate and store a first parity bit corresponding to the first data, a shadow cache memory configured to store second data with respect to the specific address, and generate and store a second parity bit corresponding to the second data, and a fault detector configured to perform a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory when receiving a data read request with respect to the specific address from a processor, and transmit the data stored in a non-erroneous memory to the processor according to a result of the parity check operation.

First claim

What is claimed is:

1. A cache control device having a fault-tolerant function, comprising:
a cache memory configured to store first data with respect to a specific address read from a main memory, and generate and store a first parity bit corresponding to the first data;
a shadow cache memory configured to store second data with respect to the specific address, and generate and store a second parity bit corresponding to the second data; and
a fault detector configured to perform a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory when receiving a data read request with respect to the specific address from a processor, and transmit the data stored in a non-erroneous memory to the processor according to a result of the parity check operation,
wherein each of the cache memory and the shadow cache memory comprises a tag memory and a data memory,
the specific address is stored in the tag memory of each of the cache memory and the shadow cache memory,
the first data and the first parity bit are stored in the data memory of the cache memory, and
the second data and the second parity bit are stored in the data memory of the shadow cache memory, and
wherein the first data and the second data are same as each other, and the first parity bit and the second parity bit are same as each other,
when the result of the parity check operation on the first data indicates that there is an error, the fault detector compares the first parity bit and the second parity bit,
when the first parity bit and the second parity bit are different from each other, the fault detector performs the parity check operation on the second data, and when there is no error in the second data, the fault detector transmits the second data to the processor, and
when the first parity bit and the second parity bit are same as each other, the fault detector outputs an error message.

2. The cache control device of claim 1 , wherein:
the first data and the second data are same as each other, and the first parity bit is different from the second parity bit,
when the result of the parity check operation on the first data indicates that there is an error, the fault detector compares the first parity bit and the second parity bit,
when the first parity bit and the second parity bit are same as each other, the fault detector performs the parity check operation on the second data, and when there is no error in the second data, the fault detector transmits the second data to the processor, and
when the first parity bit and the second parity bit are different from each other, the fault detector outputs an error message.

3. The cache control device of claim 1 , wherein the fault detector detects whether a parity of the first data and the first parity bit are same as each other, and detects whether a parity of the second data and the second parity bit are same as each other.

4. The cache control device of claim 1 , wherein the fault detector transmits the first data to the processor when the result of the parity check operation indicates that there is no error in both of the first data and the second data.

5. The cache control device of claim 1 , wherein, when the result of the parity check operation on the first data indicates that there is an error, the fault detector performs the parity check operation on the second data, and when there is no error in the second data, transmits the second data to the processor.

6. The cache control device of claim 1 , wherein, when the result of the parity check operation indicates that there is an error in both of the first data and the second data, the fault detector outputs an error message.

7. The cache control device of claim 1 , wherein the first parity bit is generated by an even parity method, and the second parity bit is generated by an odd parity method.

8. A method of preventing a fault of a cache control device, comprising:
storing first data with respect to a specific address read from a main memory and generating and storing a first parity bit corresponding to the first data, in a cache memory, and storing second data with respect to the specific address and generating and storing a second parity bit corresponding to the second data, in a shadow cache memory;
receiving a data read request with respect to the specific address from a processor; and
when receiving the data read request, performing a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory, and transmitting the data stored in a non-erroneous memory to the processor according to a result of the parity check operation,
wherein the first data and the second data are same as each other, and the first parity bit and the second parity bit are same as each other,
wherein the transmitting of the data further comprises:
when the result of the parity check operation indicates that there is an error in the first data, comparing the first parity bit and the second parity bit;
when the result of the comparing indicates that the first parity bit and the second parity bit are different from each other, performing the parity check operation on the second data; and
when the result of the parity check operation indicates that there is no error in the second data, transmitting the second data to the processor, and
wherein the transmitting of the data further comprises:
when the result of the parity check operation on the first data indicates that there is an error in the first data, comparing the first parity bit and the second parity bit; and
when the result of the comparing indicates that the first parity bit and the second parity bit are same as each other, outputting an error message.

9. The method of claim 8 ,
wherein the first data and the second data are same as each other, and the first parity bit is different from the second parity bit,
wherein the transmitting of the data further comprises:
when the result of the parity check operation, indicates that there is an error in the first data, comparing the first parity bit and the second parity bit;
when the result of the comparing indicates that the first parity bit and the second parity bit are same as each other, performing the parity check operation on the second data; and
when the result of the parity check operation indicates that there is no error in the second data, transmitting the second data to the processor,
wherein the transmitting of the data further comprises:
when the result of the parity check operation on the first data indicates that there is an error in the first data, comparing the first parity bit and the second parity bit; and
when the result of the comparing indicates that the first parity bit and the second parity bit are different from each other, outputting an error message.

10. The method of claim 8 , wherein the transmitting of the data comprises performing the parity check operation of detecting whether a parity of the first data and the first parity bit are same as each other, and detecting whether a parity of the second data and the second parity bit are same as each other.

11. The method of claim 8 , wherein the transmitting of the data comprises transmitting the first data to the processor when the result of the parity check operation indicates that there is no error in both of the first data and the second data.

12. The method of claim 8 , wherein the transmitting of the data comprises:
performing the parity check operation on the first data;
when the result of the parity check operation indicates that there is an error in

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Han Jin Ho
• Kwon Young Su

Classifications

• G06F3/064

  Management of blocks · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F11/1064 Primary

  in cache or content addressable memories · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F12/0846

  Cache with multiple tag or data arrays being simultaneously accessible · CPC title