Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping

Patent metadata

Field	Value
Publication number	US-9575119-B1
Application number	US-201615040423-A
Country	US
Kind code	B1
Filing date	Feb 10, 2016
Priority date	Oct 14, 2015
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.

First claim

What is claimed is:

1. A method of measuring a delay of an edge of a first signal with respect to an edge of a second signal within an integrated circuit, the method comprising:
controlling a frequency of a clock signal of the integrated circuit from which the first signal and the second signal are synchronously derived;
within the integrated circuit, first propagating the edge of the first signal through a tapped delay line;
within the integrated circuit, first capturing first tap positions of the edge of the first signal over multiple first measurements;
first computing a first average of the first tap positions of the edge of the first signal, wherein the controlling controls the frequency of the clock signal to determine a first frequency for which the first average of the first tap positions lies at a boundary between a pair of adjacent tap positions of the tapped delay line;
within the integrated circuit, second propagating an edge of the second signal through the tapped delay line;
within the integrated circuit, second capturing second tap positions of the edge of the second signal over multiple second measurements;
second computing an average of the second tap positions of the edge of the second signal, wherein the controlling controls the frequency of the clock signal to determine a second frequency for which the second average of the second tap positions lies at the boundary between the pair of adjacent tap positions of the tapped delay line; and
computing the delay as a difference between the periods of the first frequency and the second frequency.

2. The method of claim 1 , wherein the first signal is a signal to be measured and the second signal is a reference clock used to perform the first and second capturing.

3. The method of claim 2 , further comprising:
within the integrated circuit, third propagating an edge of a third signal to be measured that is synchronously derived from the clock signal through the tapped delay line;
within the integrated circuit, third capturing third tap positions of the edge of the third signal over multiple third measurements;
third computing an average of the third tap positions of the edge of the third signal, wherein the controlling controls the frequency of the clock signal to determine a third frequency for which the third average of the third tap positions lies at the boundary between the pair of adjacent tap positions;
computing a first delay of the first signal as a difference between the periods of the first frequency and the second frequency; and
computing a first delay of the third signal as a difference between the periods of the third frequency and the second frequency.

4. The method of claim 3 , wherein the controlling, second propagating, third propagating, second capturing and third capturing are simultaneously performed for the first signal and the third signal using two separate tapped delay circuits.

5. The method of claim 1 , wherein the clock signal of the integrated circuit is derived from an externally supplied clock, and wherein the controlling a frequency sets a frequency of the externally supplied clock.

6. The method of claim 1 , wherein the controlling a frequency sets a frequency multiplier or divider within the integrated circuit that determines the frequency of the clock signal.

7. The method of claim 1 , wherein the integrated circuit has a clock distribution network that operates in both non-resonant and resonant modes, wherein the first signal is a first clock generated in a non-resonant clocking mode of the integrated circuit, wherein the second signal to be measured is a second clock generated in a resonant clocking mode of the integrated circuit, and wherein the determining a delay further determines a latency of the first clock with respect to the second clock.

Assignees

• IBM

Inventors

• Franch Robert L
• Restle Phillip J
• Shan David Wen-Hao

Classifications

• G01R31/31725 Primary

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/2882

  Testing timing characteristics · CPC title

• G01R31/31922

  Timing generation or clock distribution (G01R31/3191 takes precedence) · CPC title