Semiconductor device comprising an output driver circuitry, a packaged semiconductor device and associated methods

US9575118B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9575118-B2
Application numberUS-201214379892-A
CountryUS
Kind codeB2
Filing dateFeb 24, 2012
Priority dateFeb 24, 2012
Publication dateFeb 21, 2017
Grant dateFeb 21, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device comprises a plurality of output pads bondable to an output pin, a plurality of reference pads bondable to a reference pin, and output driver circuitry with a control terminal for receiving a control signal and arranged to drive the plurality of output pads relative to the plurality of reference pads in dependence on the control signal. The output driver circuitry includes driver sections and selection circuitry. Each driver section is arranged to drive an output pad relative to the single reference pad in dependence on a respective section control signal. The reference pads are connected in a one-to-one relationship to the driver sections. The output pads are connected in a one-to-one relationship to the driver sections. The selection circuitry provides the respective section control signals to the driver sections in dependence on at least one selection signal and the control signal.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device for use in a package comprising an output pin and a reference pin, the semiconductor device comprising a plurality of output pads bondable to the output pin, a plurality of reference pads bondable to the reference pin, and an output driver circuitry having a control terminal for receiving a control signal and arranged to drive the plurality of output pads relative to the plurality of reference pads in dependence on the control signal, the output driver circuitry comprising a plurality of driver sections and a selection circuitry, each driver section having a driver control terminal for receiving a section control signal, a section reference terminal and a section output terminal, the section reference terminal connected to a single reference pad from the plurality of reference pads, the section output terminal connected to a single output pad from the plurality of output pads, the driver section being arranged to drive the single output pad relative to the single reference pad in dependence on the section control signal, the plurality of reference pads being connected in a one-to-one relationship to the plurality of driver sections, the plurality of output pads being connected in a one-to-one relationship to the plurality of driver sections, the selection circuitry having at least one selection input terminal for receiving at least one selection signal, a selection control terminal connected to the control terminal for receiving the control signal, a plurality of selection output terminals, each selection output terminal of the plurality of selection output terminals being connected to a respective section control terminal of a respective driver section of the plurality of driver sections and arranged to provide respective section control signals to each of the section control terminals of the plurality of driver sections in dependence on the at least one selection signal and the control signal. 2. A semiconductor device according to claim 1 , the selection circuitry being operable in a plurality of modes, the mode being selectable in dependence on the at least one selection signal, the plurality of modes comprising a test mode and a normal operation mode, the test mode corresponding to enabling driver sections of the plurality of driver sections one at a time, the normal operation mode corresponding to enabling all driver sections simultaneously. 3. A semiconductor device according to claim 1 , the plurality of driver sections consisting of two driver sections. 4. A semiconductor device according to claim 1 , the plurality of driver sections consisting of three driver sections. 5. A semiconductor device according to claim 1 , the plurality of driver sections consisting of four driver sections. 6. A semiconductor device according to claim 1 , each driver section being arranged to drive the single output pad relative to the single reference pad with an amperage in a range of 10 mA to 2 A. 7. A semiconductor device according to claim 5 , each driver section being arranged to drive the single output pad relative to the single reference pad with an amperage in a range of 100 mA to 1 A. 8. A semiconductor device according to claim 1 , each driver section comprising a power transistor connected between the section reference terminal and the section output terminal of the driver section and the section control terminal being arranged to control the power transistor. 9. A semiconductor device according to claim 1 , the selection circuitry comprising a buffer circuit for holding the at least one selection signal as lastly received by the at least one selection input terminal. 10. A packaged semiconductor device, comprising a semiconductor device according to claim 1 and a package having an output pin and a reference pin, the output pin being connected to all output pads of the plurality of output pads of the semiconductor device and the reference pin being connected to all reference pads of the plurality of reference pads of the semiconductor device. 11. A packaged semiconductor device according to claim 10 , the output pin being connected to all output pads using a plurality of bond wires, each bond wire connecting one of the output pads to the output pin, and the reference pin being connected to all reference pads using a plurality of further bond wires, each further bond wire connecting one of the reference pads to the reference pin. 12. A packaged semiconductor device according to claim 10 , the output pin being connected to all output pads using a plurality of bond bumps and the reference pin being connected to all reference pads using a plurality of further bond bumps. 13. A method of testing a packaged semiconductor device and a package having an output pin and a reference pin, the method comprising: conditioning and providing a selection signal to a selection input terminal of the selection circuitry to select a single driver section of a plurality of driver sections, conditioning and providing a control signal to a control terminal of an output driver circuitry to activate the single driver section, and testing a conductivity between an output pin and an reference pin, the testing comprising obtaining a measure of a conductivity and comparing the measure conductivity against a pre-determined threshold level to obtain a comparison result; and concluding whether the output pin is connected to all output pads of a plurality of output pads of the semiconductor device and a reference pin is connected to all reference pads of a plurality of reference pads of the semiconductor device. 14. The method of claim 13 , the method further comprising: conditioning and providing the selection signal to the at least one selection input terminal of the selection circuitry to select all driver sections of the plurality of driver sections. 15. The method of claim 13 , the method further comprising: in response to the selection signal having a first value, operating the packaged semiconductor device in a test mode to enable driver sections of the plurality of driver sections one at a time; and in response to the selection signal having a second value, operating the packaged semiconductor device in a normal operation mode to enable all driver sections simultaneously. 16. The method of claim 13 , further comprising: driving, by each driver section, the single output pad relative to the single reference pad with an amperage in a range of 10 mA to 2 A. 17. The method of claim 13 , further comprising: driving, by each driver section, the single output pad relative to the single reference pad with an amperage in a range of 100 mA to 1 A. 18. A semiconductor device for use in a package comprising an output pin and a reference pin, the semiconductor device comprising: a plurality of output pads bondable to the output pin; a plurality of reference pads bondable to the reference pin; and an output driver circuitry having a control terminal to receive a control signal, the output driver circuitry to drive the plurality of output pads relative to the plurality of reference pads based on the control signal, the output driver circuitry comprising: a plurality of drivers comprising first and second drivers, the first driver having a first driver control terminal to receive a first control signal, a first reference terminal and a first output terminal, the first reference terminal connected to a first reference pad from the plurality of reference pads, the first output terminal connected to a first output pad from the plurality of

Assignees

Inventors

Classifications

  • multiple bond wires connected to a common bond pad · CPC title

  • Plan-view shape, i.e. in top view · CPC title

  • H10W72/90Primary

    Bond pads, in general · CPC title

  • Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00) · CPC title

  • as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic · CPC title

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What does patent US9575118B2 cover?
A semiconductor device comprises a plurality of output pads bondable to an output pin, a plurality of reference pads bondable to a reference pin, and output driver circuitry with a control terminal for receiving a control signal and arranged to drive the plurality of output pads relative to the plurality of reference pads in dependence on the control signal. The output driver circuitry includes…
Who is the assignee on this patent?
Bode Hubert, Nxp Usa Inc
What technology area does this patent fall under?
Primary CPC classification H10W72/90. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 21 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).