Convolution-encoded hyper-speed channel with robust trellis error-correction

Patent metadata

Field	Value
Publication number	US-9571126-B2
Application number	US-201615095379-A
Country	US
Kind code	B2
Filing date	Apr 11, 2016
Priority date	May 19, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A method, system, and computer program product for performing robust, parallel data transfer by a processor device. Data is segmented into k-bit segments, where k≧1. The k-bit segments are convolution encoded, using m≧1 stages of delay. The n output streams are transmitted in parallel for increased effective data rate, where n>k. The n output streams are received. An XOR (Exclusive OR) logic is applied to the n output streams with pathing allowed by the convolution encoding, in a trellis-decoding diagram.

First claim

The invention claimed is:

1. A method for performing robust, parallel data transfer by a processor device, comprising:
segmenting data into k-bit segments, where k≧1;
convolution encoding the k-bit segments, using m≧1 stages of delay;
transmitting n output streams in parallel for increased effective data rate, where n>k;
receiving the n output streams; and
applying an XOR (Exclusive OR) logic to the n output streams with pathing allowed by the convolution encoding, in a trellis-decoding diagram.

2. The method of claim 1 , further including at least one of:
identifying error-corrected data as an overall path with zero Hamming radius,
identifying each packet of the data by sequence number and which output port of a convolution encoder the packet originated, and
reassembling transmitted packets based on the sequence number and the output port.

3. The method of claim 1 , further including generating 2 km states, with 2 k branches entering each state, and 2 k branches leaving each state.

4. The method of claim 1 , further including sending each of the n output streams to a separate Cloud for storage.

5. The method of claim 1 , wherein transmitting the output streams further includes transmitting each of the output streams along a discrete link for communication.

6. The method of claim 5 , wherein transmitting each of the output streams along a discrete link for communication includes transmitting along one of a separate gigabit Ethernet network (GbEN) link, a Fibre Channel (FC) link, a Fibre Channel over Ethernet (FCoE) link, an Infiniband link, a Small Computer Systems Interface (SCSI) link, and an Internet Small Computer Systems Interface (iSCSI) link.

7. A system for performing robust, parallel data transfer, comprising:
a processor device that:
segments data into k-bit segments, where k≧1;
convolution encodes the k-bit segments, using m≧1 stages of delay;
transmits n output streams in parallel for increased effective data rate, where n>k;
receives the n output streams; and
applies an XOR (Exclusive OR) logic to the n output streams with pathing allowed by the convolution encoding, in a trellis decoding diagram.

8. The system of claim 7 , further including a convolution encoder in operable communication with the processor device, wherein the convolution encoder encodes the k-bit segments.

9. The system of claim 7 , wherein the processor device at least one of:
identifies error-corrected data as an overall path with zero Hamming radius,
identifies each packet of the data by sequence number and which output port of a convolution encoder the packet originated, and
reassembles transmitted packets based on the sequence number and the output port.

10. The system of claim 7 , wherein the processor device generates 2 km states, with 2 k branches entering each state, and 2 k branches leaving each state.

11. The system of claim 7 , wherein the processor device sends each of the n output streams to a separate Cloud for storage.

12. The system of claim 7 , wherein the processor device, pursuant to transmitting the output streams, transmits each of the output streams along a discrete link for communication.

13. The system of claim 11 , wherein the discrete link further includes one of a separate gigabit Ethernet network (GbEN) link, a Fibre Channel (FC) link, a Fibre Channel over Ethernet (FCoE) link, an Infiniband link, a Small Computer Systems Interface (SCSI) link, and an Internet Small Computer Systems Interface (iSCSI) link.

14. A computer program product for performing robust, parallel data transfer by a processor device, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising:
a first executable portion that segments data into k-bit segments, where k≧1;
a second executable portion that convolution encodes the k-bit segments, using m≧1 stages of delay;
a third executable portion that transmits n output streams in parallel for increased effective data rate, where n>k;
a fourth executable portion that receives the n output streams; and
a fifth executable portion that applies an XOR (Exclusive OR) logic to the n output streams with pathing allowed by the convolution encoding, in a trellis decoding diagram.

15. The computer program product of claim 14 , further including a sixth executable portion that at least one of:
identifies error-corrected data as an overall path with zero Hamming radius,
identifies each packet of the data by sequence number and which output port of a convolution encoder the packet originated, and
reassembles transmitted packets based on the sequence number and the output port.

16. The computer program product of claim 14 , further including a sixth executable portion that generates 2 km states, with 2 k branches entering each state, and 2 k branches leaving each state.

17. The computer program product of claim 14 , further including a sixth executable portion that sends each of the n output streams to a separate Cloud for storage.

18. The computer program product of claim 14 , further including a sixth executable portion that, pursuant to transmitting the output streams, transmits each of the output streams along a discrete link for communication.

19. The computer program product of claim 18 , further including a seventh executable portion for, pursuant to transmitting each of the output streams along a discrete link for communication, transmitting along one of a separate gigabit Ethernet network (GbEN) link, a Fibre Channel (FC) link, a Fibre Channel over Ethernet (FCoE) link, an Infiniband link, a Small Computer Systems Interface (SCSI) link, and an Internet Small Computer Systems Interface (iSCSI) link.

Assignees

• IBM

Inventors

• Astigarraga Tara
• Dickens Louie A
• Hocker Michael D
• Starling Michael E
• Winarski Daniel J

Classifications

• H03M13/256 Primary

  with trellis coding, e.g. with convolutional codes and TCM · CPC title

• H03M13/3961

  Arrangements of methods for branch or transition metric calculation · CPC title

• H03M13/39

  Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title

• H03M13/25 Primary

  Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] {(modulation codes H03M13/31)} · CPC title