Digital to analog converter circuits, apparatus and method for generating a high frequency transmission signal and methods of digital to analog conversion

Patent metadata

Field	Value
Publication number	US-9571120-B2
Application number	US-201514835031-A
Country	US
Kind code	B2
Filing date	Aug 25, 2015
Priority date	Sep 25, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

First claim

What is claimed is:

1. A digital to analog converter circuit comprising:
a plurality of digital to analog converter cells; and
a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

2. The digital to analog converter circuit according to claim 1 , wherein each digital to analog converter cell of the plurality of digital to analog converter cells is assigned to a cell row of a plurality of cell rows and a cell column of a plurality of cell columns.

3. The digital to analog converter circuit according to claim 1 , wherein the control circuit comprises a decoder control circuit configured to control a column operation mode of a column of digital to analog converter cells.

4. The digital to analog converter circuit according to claim 3 , wherein the decoder control circuit is configured to control the column operation mode of a column of digital to analog converter cells based on a first column code derived from at least part of the first phase component of the digital signal and based on a second column code derived from at least part of the second phase component of the digital signal.

5. The digital to analog converter circuit according to claim 4 , wherein the decoder control circuit comprises a first column decoder circuit configured to derive the first column code based on at least part of the first phase component of the digital signal and a second column decoder circuit configured to derive the second column code based on at least part of the second phase component of the digital signal.

6. The digital to analog converter circuit according to claim 5 , wherein the first column decoder circuit is configured to derive the first column code based on most significant bits of the first phase component of the digital signal, and wherein the second column decoder circuit is configured to derive the second column code based on most significant bits of the second phase component of the digital signal.

7. The digital to analog converter circuit according to claim 5 , wherein the decoder control circuit comprises an XOR gate or OR gate associated with a cell column of a plurality of cell columns, wherein the XOR gate or OR gate is coupled to the first column decoder circuit and the second column decoder circuit, wherein an output signal of the XOR gate or OR gate indicates a column operation mode of the cell column.

8. The digital to analog converter circuit according to claim 3 , wherein the decoder control circuit is configured to provide a last column signal indicating a last column of digital to analog converter cells operating in a first column operation mode and a last column signal indicating a last column of digital to analog converter cells operating in a second operation mode.

9. The digital to analog converter circuit according to claim 3 , comprising at least one inactive column of digital to analog converter cells located between the last column of digital to analog converter cells operating in the first column operation mode and the last column of digital to analog converter cells operating in the second column operation mode.

10. The digital to analog converter circuit according to claim 1 , wherein the control circuit further comprises a first row decoder circuit configured to derive a first row code based on at least part of the first phase component of the digital signal and a second row decoder circuit configured to derive a second row code based on at least part of the second phase component of the digital signal.

11. The digital to analog converter circuit according to claim 1 , wherein the control circuit comprises a local activation control circuit configured to control an activation of a digital to analog converter cell in a column of digital to analog converter cells.

12. The digital to analog converter circuit according to claim 11 , wherein the local activation control circuit is configured to control an activation of the digital to analog converter cell based on the column operation mode and at least one of the first row code and the second row code or without consideration of the first row code or second row code.

13. The digital to analog converter circuit according to claim 11 , wherein the local activation control circuit is configured to switch the digital to analog converter cell with a frequency of an oscillator signal if the digital to analog converter cell is activated.

14. The digital to analog converter circuit according to claim 1 , wherein the control circuit comprises an oscillator circuit configured to generate a first oscillator signal and a second oscillator signal, wherein the first oscillator signal and the second oscillator signal comprise a same frequency representing a carrier frequency to be used to transmit the information to be transmitted and comprise a predefined phase offset.

15. The digital to analog converter circuit according to claim 14 , wherein the control circuit is configured to provide the first oscillator signal to a column of digital to analog converter cells operating in a first column operation mode and the second oscillator signal to a column of digital to analog converter cells operating in a second column operation mode.

16. The digital to analog converter circuit according to claim 1 , wherein the digital to analog converter cells of the plurality of digital to analog converter cells each comprise a switchable current source or a switchable capacitive element to produce a cell analog output signal having a first analog output state or a second analog output state.

17. An apparatus for generating a high frequency transmission signal, comprising:
a signal converter configured to generate a first adapted phase component and a second adapted phase component of a digital signal comprising information to be transmitted derivable by a rotation transformation of a first and a second input phase component of a digital signal; and
an up conversion module configured to generate a high frequency transmission signal based on the first adapted phase component and the second adapted phase component of the digital signal.

18. The apparatus according to claim 17 , wherein the up conversion module comprises a digital to analog converter circuit comprising:
a plurality of digital to analog converter cells; and
a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

19. The apparatus according to claim 18 , wherein the control circuit comprises a decoder control circuit configured to control a column operation mode of a column of digital to analog converter cells.

20. The apparatus according to claim 17 , further comprising a conversion correction circuit configured to correct a sign error of at least one of the first adapted phase component and the second adapted phase component based on a value of the first adapted phase component and the second adapted phase component.

21. A digital to

Assignees

• Intel Ip Corp

Inventors

• Kuttner Franz
• Passamani Antonio
• Ponton Davide

Classifications

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/662 Primary

  Multiplexed conversion systems · CPC title

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title

• H03M1/74

  Simultaneous conversion · CPC title