Multi-output phase detector

Patent metadata

Field	Value
Publication number	US-9571108-B2
Application number	US-201414543783-A
Country	US
Kind code	B2
Filing date	Nov 17, 2014
Priority date	Oct 13, 2012
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Representative implementations of devices and techniques provide a multi-bit binary representation of a phase difference between two signals. The multi-bit binary representation may include information regarding a sign of the phase difference and a magnitude of the phase difference.

First claim

What is claimed is:

1. A system, comprising:
a digitally-controlled oscillator (DCO), arranged to produce an output signal having a frequency proportional to a value of a digital control word;
a feedback divider arranged to provide a modified clock signal based on the output signal;
a multi-output phase detector arranged to sense a phase difference between a reference clock signal and the modified clock signal and to output a multi-bit representation of the phase difference; and
a digital loop filter arranged to form the digital control word based on the multi-bit representation.

2. The system of claim 1 , wherein the multi-output phase detector is arranged to detect whether and to what extent a phase of the reference clock signal leads or lags a phase of the modified clock signal.

3. The system of claim 1 , wherein the multi-bit representation comprises a binary word of predetermined length and includes information about a polarity of the phase difference and a magnitude of the phase difference.

4. A method, comprising:
receiving a clock signal;
receiving a reference clock signal;
sensing a phase difference between the reference clock signal and the clock signal;
determining a sign and a magnitude of the phase difference;
outputting a multi-bit binary representation of the phase difference.

5. The method of claim 4 , further comprising determining whether and to what extent the reference clock signal leads or lags the clock signal.

6. The method of claim 4 , further comprising comparing the phase difference to a delay value of one or more delay components, the one or more delay components representing a predetermined phase-mismatch range.

7. The method of claim 6 , further comprising outputting the multi-bit binary representation based on summing delay values of a quantity of the one or more delay components.

8. The method of claim 6 , further comprising programming and/or adjusting the delay value of the one or more delay components.

9. The method of claim 4 , further comprising outputting a binary representation of the phase difference that includes information about a sign of the phase difference and a magnitude of the phase difference.

10. The method of claim 4 , further comprising outputting the multi-bit binary representation in parallel from a plurality of individual binary phase detectors.

11. The method of claim 4 , further comprising forming a digital control word based on the binary representation of the phase difference, the digital control word arranged to determine an output frequency of a digitally controlled oscillator, wherein the output frequency is proportional to a numerical value of the digital control word.

12. The method of claim 11 , wherein the clock signal is derived from the output frequency of the digitally controlled oscillator.

13. A device, comprising:
a plurality of delay components coupled to a first input of the device, one or more of the delay components having a delay value that is programmable and/or adjustable; and
a plurality of components coupled to the plurality of delay components and coupled to a second input of the device, the plurality of components having a plurality of outputs arranged to output a binary representation of a phase difference between a signal at the first input of the device and another signal at the second input of the device.

14. The device of claim 13 , wherein the delay components are arranged in series, and delay values of each of the delay components are substantially equal.

15. The device of claim 14 , wherein the binary representation of the phase difference is at least in part a result of summing the delay values of a quantity of the delay components, the quantity of the delay components summed being proportional to a magnitude of the phase difference.

16. The device of claim 15 , wherein the delay components comprise CMOS buffers with substantially equal capacitive loads.

17. The device of claim 13 , wherein the delay components are arranged in parallel, and delay values of each of the delay components are substantially different from each other.

18. The device of claim 17 , wherein the binary representation of the phase difference is a result of a comparison of the phase difference to a delay value of one or more of the delay components.

19. The device of claim 17 , wherein the delay components comprise CMOS buffers with different capacitive loads.

20. The device of claim 13 , wherein each of the plurality of devices comprises a single binary sampling circuit.

21. The device of claim 13 , wherein the device is arranged to detect whether and to what extent the signal at the first input is leading or lagging the other signal at the second input.

22. The device of claim 13 , wherein the binary representation of the phase difference includes information about a sign of the phase difference and a magnitude of the phase difference.

Assignees

• Infineon Technologies Ag

Inventors

• Nonis Roberto
• Dadalt Nicola
• Thaller Edwin

Classifications

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/091 Primary

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03K2005/00058

  controlled by a digital setting · CPC title