Bidirectional delay circuit and integrated circuit including the same

Patent metadata

Field	Value
Publication number	US-9571076-B2
Application number	US-201514877258-A
Country	US
Kind code	B2
Filing date	Oct 7, 2015
Priority date	Oct 14, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal.

First claim

What is claimed is:

1. A bidirectional delay circuit comprising:
an input driving circuit connected between an input node and an intermediate node, the input driving circuit configured to amplify an input signal received through the input node and to generate an intermediate signal through the intermediate node; and
a delay switch circuit connected between the intermediate node and a delay node, the delay switch circuit configured to delay both of rising edges and falling edges of the intermediate signal in response to a gate signal and to generate a delay signal through the delay node, the gate signal transitioning in response to the input signal.

2. The bidirectional delay circuit of claim 1 , wherein the delay switch circuit includes:
a P-type transistor connected between the intermediate node and the delay node, the P-type transistor including a P-type gate electrode receiving the gate signal; and
an N-type transistor connected between the intermediate node and the delay node, the N-type transistor including an N-type gate electrode receiving the gate signal.

3. The bidirectional delay circuit of claim 2 , wherein, in response to a logic level of the gate signal, one of the P-type transistor and the N-type transistor is turned on and the other of the P-type transistor and the N-type transistor is turned off.

4. The bidirectional delay circuit of claim 2 , wherein the P-type gate electrode and the N-type gate electrode are electrically connected to the input node through a conduction path.

5. The bidirectional delay circuit of claim 4 , wherein the conduction path includes a gate poly that is formed and patterned together with the P-type gate electrode and the N-type gate electrode.

6. The bidirectional delay circuit of claim 2 , wherein the P-type gate electrode and the N-type gate electrode are electrically connected to the intermediate node through a conduction path.

7. The bidirectional delay circuit of claim 1 , wherein the input driver circuit includes one or more gate circuits that are connected in series between the input node and the intermediate node, and
the delay switch circuit includes one or more transmission gates that are connected in series between the intermediate node and the delay node, each transmission gate including a P-type gate electrode and an N-type gate electrode that receive the gate signal.

8. The bidirectional delay circuit of claim 7 , wherein the gate circuits include at least one of an inverter, a buffer, an AND gate, an OR gate, a NAND gate, a NOR gate, an exclusive OR gate and an exclusive NOR gate.

9. The bidirectional delay circuit of claim 7 , wherein, with respect to the one or more transmission gates, the P-type gate electrode and the N-type electrode are electrically connected to the input node.

10. The bidirectional delay circuit of claim 7 , wherein, with respect to the one or more transmission gates, the P-type gate electrode and the N-type electrode are electrically connected to the intermediate node.

11. The bidirectional delay circuit of claim 1 , further comprising an output driving circuit connected between the delay node and an output node, the output circuit configured to amplify the delay signal and to generate an output signal through the output node.

12. The bidirectional delay circuit of claim 1 , further comprising a gate signal generator configured to be powered by a first voltage and a second voltage which is lower than the first voltage, and configured to generate the gate signal transitioning between a first gate voltage and a second gate voltage, the first gate voltage being lower than the first voltage, the second gate voltage being higher than the second voltage.

13. The bidirectional delay circuit of claim 12 , wherein the gate signal generator includes:
a first voltage generator configured to generate the first gate voltage;
a second voltage generator configured to generate the second gate voltage; and
an output switch circuit configured to select one of the first gate voltage and the second gate voltage and to output the gate signal.

14. The bidirectional delay circuit of claim 13 , wherein the first voltage generator includes a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor sequentially connected in series from the first voltage to the second voltage,
the second voltage is applied to gate electrodes of the first P-type transistor and the second P-type transistor,
the first gate voltage is provided through a connection node of the first P-type transistor and the second P-type transistor,
the input signal is applied to a gate electrode of the first N-type transistor, and
an enable signal is applied to a gate electrode of the second N-type transistor.

15. The bidirectional delay circuit of claim 14 , wherein the second voltage generator includes a third N-type transistor, a fourth N-type transistor, a third P-type transistor and a fourth P-type transistor sequentially connected in series from the second voltage to the first voltage,
the first voltage is applied to gate electrodes of the third N-type transistor and the fourth N-type transistor,
the second gate voltage is provided through a connection node of the third N-type transistor and the fourth N-type transistor,
the input signal is applied to a gate electrode of the third P-type transistor, and
an inversion signal of the enable signal is applied to a gate electrode of the fourth P-type transistor.

16. The bidirectional delay circuit of claim 13 , wherein the output switch circuit includes:
a first output switch configured to provide the first gate voltage as a voltage level of the gate signal according to the input signal; and
a second output switch configured to provide the second gate voltage as the voltage level of the gate signal according to the input signal.

17. An integrated circuit comprising:
a plurality of bidirectional delay circuits that are cascade-coupled, each of the plurality of bidirectional delay circuits configured to receive a delay signal from the bidirectional delay circuit of a previous stage as an input signal, each bidirectional delay circuit comprising:
an input driving circuit connected between an input node and an intermediate node, the input driving circuit configured to amplify the input signal received through the input node, and to generate an intermediate signal through the intermediate node; and
a delay switch circuit connected between the intermediate node and a delay node, the delay switch circuit configured to delay both of rising edges and falling edges of the intermediate signal in response to a gate signal, and to generate the delay signal through the delay node, the gate signal transitioning in response to the input signal.

18. The integrated circuit of claim 17 , wherein the delay switch circuit includes:
a P-type transistor connected between the intermediate node and the delay node, the P-type transistor including a P-type gate electrode receiving the gate signal; and
an N-type transistor connected between the intermediate node and the delay node, the N-type transistor including an N-type gate electrode receiving the gate signal.

19. The integrated circuit of claim 17 , wherein the plurality of bidirectional delay circuits include:
a first bidirectional delay circuit configured to delay a first input signal in response to a first gate signal, and to generate a first delay signal; and
a second bidirectional delay circuit configured to receive the first delay signal as a second inpu

Assignees

• Seo Jae-Woo
• Park Sung-Hyun
• Rim Woo-Jin
• Kim Ha-Young
• Lee Jae-Ha
• Kim Yong-Ho
• Samsung Electronics Co Ltd

Inventors

• Seo Jae-Woo
• Park Sung-Hyun
• Rim Woo-Jin
• Kim Ha-Young
• Lee Jae-Ha
• Kim Yong-Ho

Classifications

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03K5/12 Primary

  by steepening leading or trailing edges · CPC title

• H03K5/13

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H03K2005/00215

  where the conduction path of multiple FET's is in parallel or in series, all having the same gate control · CPC title