Implementing enhanced bias configuration for CMOS inverter based optical Transimpedance Amplifier

Patent metadata

Field	Value
Publication number	US-9571050-B2
Application number	US-201514696420-A
Country	US
Kind code	B2
Filing date	Apr 25, 2015
Priority date	Feb 2, 2015
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A method and circuit are provided for implementing an enhanced bias configuration for CMOS inverter based optical Transimpedance Amplifiers (TIAs). An operational amplifier is provided in a feedback configuration that forces an input of the CMOS inverter to a set voltage level by regulation of the inverter power supply. A photo-detector sees a more stable bias voltage, and the responsivity of the photo-detector is more robust and the TIA has improved performance across process corners.

First claim

What is claimed is:

1. A method for implementing an enhanced bias configuration for CMOS inverter based optical Transimpedance Amplifiers (TIAs) comprising the steps of:
providing a Transimpedance Amplifier (TIA) and a replica TIA by forming said TIA by an inverter and a first feedback resistor and a photo-detector input, and forming said replica TIA by a replica inverter with a second feedback resistor;
providing a voltage divider formed by series connected resistors connected between a voltage rail VDD and a ground rail for generating a first set voltage level;
providing a first input of said operational amplifier with said first set voltage level;
providing an operational amplifier in a feedback configuration for regulating a second set voltage level at the photo-detector input of said TIA; and providing said Transimpedance Amplifier (TIA) and a replica TIA includes providing each of said TIA and replica TIA formed by a series connected P-channel field effect transistor (PFET) and N-channel field effect transistor (NFET) and said associated feedback resistor.

2. The method as recited in claim 1 wherein providing an operational amplifier in a feedback configuration for regulating a second set voltage level at the photo-detector input of said TIA includes providing said operational amplifier with a first input receiving said second set voltage level and a second input receiving an input of said replica TIA.

3. The method as recited in claim 2 includes providing a field effect transistor (FET) receiving a gate input from an output of said operational amplifier and said FET providing a voltage reference to said TIA and said replica TIA.

4. The method as recited in claim 3 wherein providing said FET receiving a gate input from an output of said operational amplifier includes providing an N-channel field effect transistor (NFET) connected between a ground rail and a common source connection of said TIA NFET and said replica TIA NFET.

5. The method as recited in claim 3 wherein providing said FET receiving a gate input from an output of said operational amplifier includes providing a P-channel field effect transistor (PFET) connected between a voltage rail VDD and a common source connection of said TIA PFET and said replica TIA PFET.

Assignees

• IBM

Inventors

• Frank Matthew B
• Proesel Jonathan E
• Richetta Raymond A

Classifications

• H03F2200/153

  Feedback used to stabilise the amplifier · CPC title

• H03F2203/45264

  the dif amp comprising frequency or phase stabilisation means · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F3/082 Primary

  with FET's (H03F3/085 takes precedence) · CPC title

• H03F3/45179 Primary

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title