Method and processing apparatus for fabricating a magnetic resistive random access memory device

Patent metadata

Field	Value
Publication number	US-9570673-B2
Application number	US-201514794796-A
Country	US
Kind code	B2
Filing date	Jul 8, 2015
Priority date	Nov 18, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Methods of fabricating MRAM devices are provided along with a processing apparatus for fabricating the MRAM devices. The methods may include forming a ferromagnetic layer, cooling the ferromagnetic layer to a temperature within a range of between about 50° K to about 300° K, forming and oxidizing one or more Mg layers on the cooled ferromagnetic layer to form an MgO structure, forming a free layer on the MgO structure, and forming a capping layer on the free layer.

First claim

What is claimed is:

1. A method of fabricating a magnetic resistive random access memory (MRAM) device, the method comprising:
forming a lower electrode on a substrate;
forming a seed layer on the lower electrode;
forming a pinning layer on the seed layer;
forming a synthetic anti-ferromagnetic (SAF) layer on the pinning layer;
forming a pinned layer on the SAF layer;
cooling the substrate having the pinned layer exposed thereon to a range of approximately between about 50° K to about 300° K;
forming a first Mg layer on the cooled pinned layer;
forming a first MgO layer by oxidizing the first Mg layer;
forming a second Mg layer on the first MgO layer;
forming a second MgO layer by oxidizing the second Mg layer, wherein the first and second MgO layers collectively form an MgO structure;
forming a free layer on the MgO structure;
forming a capping layer on the free layer; and
forming an upper electrode on the capping layer.

2. The method of claim 1 , wherein the seed layer comprises at least one of Ta or Ru.

3. The method of claim 2 , wherein the seed layer comprises a lower Ta layer and an upper Ru layer stacked on the lower Ta layer.

4. The method of claim 1 , wherein the pinning layer comprises a CoPt-based alloy or CoPd-based alloy having a hexagonal closest packing (HCP) structure.

5. The method of claim 1 , wherein the pinning layer comprises a stacked layer of Co/Pt or Co/Pd having a face center cubic (FCC) structure or FCC-like structures.

6. The method of claim 1 , wherein the SAF layer comprises Ru.

7. The method of claim 1 , wherein the pinned layer comprises CoFeB.

8. The method of claim 7 , wherein the pinned layer comprises one of multilayer structures including CoFeB/Ta/CoFeB, Co/B/CoFeB, or Co/W/CoFeB/W/CoFeB.

9. The method of claim 1 , wherein the free layer comprises a single layer including CoFeB, or a multilayer including CoFeB/W/CoFeB.

10. The method of claim 1 , wherein the capping layer comprises a metal such as Ta.

11. The method of claim 1 , further comprising:
forming a third Mg layer between the second MgO layer and the free layer; and
forming a third MgO layer by oxidizing the third Mg layer.

12. The method of claim 11 , wherein the first MgO layer, the second MgO layer, and the third MgO layer are unified to be materially contiguous with each other.

13. The method of claim 11 , further comprising cooling the second MgO layer before forming the third Mg layer thereon.

14. The method of claim 1 , further comprising cooling the first MgO layer before forming the second Mg layer thereon.

15. A method of fabricating an MRAM device, the method comprising:
forming a lower electrode on a substrate;
forming a seed layer having Ta and Ru on a lower electrode;
forming a pinning layer having Co on the seed layer;
forming an SAF layer having Ru on the pinning layer;
forming an pinned layer having CoFe on the SAF layer;
cooling the substrate having the pinned layer exposed thereon to a range of approximately between about 50° K to about 300° K;
forming a first Mg layer on the cooled pinned layer;
forming a first MgO layer by oxidizing the first MgO layer;
forming a second Mg layer on the first MgO layer;
forming a second MgO layer by oxidizing the second Mg layer;
forming a free layer having CoFeB on the second MgO layer;
forming a capping layer having Ta on the free layer; and
forming an upper electrode on the capping layer.

16. A method of fabricating an MRAM device, the method comprising:
forming a gate structure on a substrate;
forming a source region and a drain region in the substrate adjacent to opposite sides of the gate structure;
forming a source contact plug connected with the source region, and a source interconnection connected with the source plug;
forming a lower electrode connected with the drain region;
forming a ferromagnetic layer on the lower electrode;
cooling the substrate having the ferromagnetic layer exposed thereon to a range of approximately between about 50° K to about 300° K;
forming a first Mg layer on the cooled ferromagnetic layer;
forming a first MgO layer by oxidizing the first Mg layer;
forming a second Mg layer on the first MgO layer,
forming a second MgO layer by oxidizing the second Mg layer;
forming a third Mg layer on the second MgO layer;
forming a third MgO layer by oxidizing the third Mg layer;
forming a free layer on the third MgO layer; and
forming a capping layer on the free layer.

17. The method of claim 16 , further comprising:
forming a lower interlayer insulting layer covering the gate structure,
wherein the source contact plug vertically passes through the lower interlayer insulating layer, and
wherein the source interconnection is formed on the lower interlayer insulating layer.

18. The method of claim 17 , further comprising:
forming a drain contact plug vertically passing through the lower interlayer insulating layer to be connected with the drain region;
forming a lower electrode pad on the lower interlayer insulating layer to be connected with the drain contact plug; and
forming a middle interlayer insulating layer covering the source interconnection and the lower electrode pad,
wherein the lower electrode vertically passes through the middle interlayer insulating layer to be connected with the lower electrode pad.

19. The method of claim 16 , further comprising:
forming a fourth Mg layer on the third MgO layer, and oxidizing the fourth Mg layer to form a fourth MgO layer before forming the free layer, wherein the free layer is formed on the fourth MgO layer;
forming a liner layer on sidewalls of the ferromagnetic layer, the first to fourth MgO layers, the free layer, and the capping layer and a top surface of the capping layer;
forming an upper electrode passing through the liner layer to be in contact with the capping layer; and
forming a bit line on the upper electrode.

20. The method of claim 19 , wherein forming the upper electrode comprises:
removing the liner layer to completely expose the top surface of the capping layer and to at least partially expose upper portions of the sidewalls of the capping layer,
wherein the upper electrode is formed in contact with the exposed top surface and the exposed upper portions of the sidewalls of the capping layer.

Assignees

• Park Yongsung
• Kim Kiwoong
• Kim Sangyong
• Oh Sechung
• Jang Youngman
• Samsung Electronics Co Ltd

Inventors

• Park Yongsung
• Kim Kiwoong
• Kim Sangyong
• Oh Sechung
• Jang Youngman

Classifications

• H01L27/224

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H01L43/08 Primary

  Electricity · mapped topic