Magnetoresistive random access memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9570510-B2
Application number	US-201514724725-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	Jul 18, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other. MTJ structures may be electrically connected to corresponding ones of the second semiconductor patterns. Each bit line structure may electrically connect two adjacent MTJ structures in the first direction to each other.

First claim

What is claimed is:

1. A magnetoresistive random access memory device, comprising:
a plurality of semiconductor structures arranged on a substrate, wherein each of the semiconductor structures includes a first semiconductor pattern and second semiconductor patterns on the first semiconductor pattern, the first semiconductor pattern having a substantially linear shape extending in a first direction, wherein the first direction is substantially parallel to a top surface of the substrate, each of the second semiconductor patterns extending in a third direction, wherein the third direction is substantially perpendicular to the top surface of the substrate, and the plurality of semiconductor structures being arranged in a second direction, wherein the second direction is substantially perpendicular to both the first direction and the third direction;
a common source region, a drain region, and a channel region provided in each of the semiconductor structures, wherein a corresponding common source region and drain region are spaced apart from each other in the third direction, and wherein a corresponding channel region is arranged between the corresponding common source and drain regions;
a plurality of gate structures, wherein a single gate structure is arranged between at least two second semiconductor patterns that are adjacent to each other in the second direction, such that each of the gate structures serves as a common gate electrode for corresponding second semiconductor patterns;
a plurality of word line structures, each word line structure electrically connecting multiple gate structures arranged in the first direction to each other;
a plurality of MTJ structures, each MTJ structure electrically connected to an upper portion of a corresponding one of the second semiconductor patterns; and
a plurality of bit line structures, wherein each of the bit line structures is electrically connected to two MTJ structures adjacent to each other in the first direction, each of the bit line structures extends in the second direction, and is also electrically connected a plurality of MTJ structure groups arranged in the second direction, wherein each pair of electrically connected adjacent MTJ structures forms an MTJ structure group.

2. The device of claim 1 , wherein each of the gate structures has a substantially pillar shape.

3. The device of claim 1 , wherein each of the gate structures includes a gate insulation layer and a gate electrode, and wherein the gate insulation layer contacts sidewalls of the semiconductor structures adjacent to each other in the second direction, and wherein the gate insulation layer further has a substantially cup-like shape surrounding a sidewall and a lower surface of the gate electrode.

4. The device of claim 1 , wherein the second semiconductor patterns each include third semiconductor patterns abutting the gate structures in the second direction and fourth semiconductor patterns not abutting the gate structures in the second direction, wherein the third and fourth semiconductor patterns are alternately disposed in the first direction.

5. The device of claim 1 , wherein bottom surfaces of the gate structures are substantially coplanar with, or lower than, an upper surface of the common source region.

6. The device of claim 1 , wherein each of the word line structures extends on the gate structures in the first direction.

7. The device of claim 1 , wherein the common source region and the drain region are doped with impurities having a first conductivity type, and wherein the common source region is formed extending in the first direction in the first semiconductor pattern, and wherein the drain region is formed at an upper portion of the second semiconductor pattern.

8. The device of claim 7 , wherein the channel region is formed in the second semiconductor pattern between the common source region and the drain region, and wherein the channel region is doped with impurities having a second conductivity type that is different from the first conductivity type.

9. The device of claim 7 , further comprising a channel body region arranged on the common source region of the first semiconductor pattern, wherein the channel body region is electrically connected to a lower portion of the channel region and extends in the first direction, and wherein the channel body region is doped with impurities having a second conductivity type that is different from the first conductivity type.

10. The device of claim 7 , wherein the common source region is formed at sidewalls of the first semiconductor pattern, and wherein the device further comprises:
a channel body region arranged in the first semiconductor pattern between the common source lines, wherein the channel body region is electrically connected to a lower portion of the channel region and extends in the first direction, and wherein the channel body is doped with impurities having a second conductivity type that is different from the first conductivity type.

11. The device of claim 1 , further comprising:
pad patterns arranged on the MTJ structures, wherein each of the pad patterns electrically connects the two adjacent MTJ structures in the first direction; and
upper contacts arranged on the pad patterns to contact the bit line.

12. The device of claim 11 , wherein the pad patterns are disposed in a zigzag fashion in the first direction when viewed in a plan view.

13. A magnetoresistive random access memory, comprising:
semiconductor structures arranged on a substrate, each of the semiconductor structures including a first semiconductor pattern and second semiconductor patterns on the first semiconductor pattern, wherein the first semiconductor pattern has a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, wherein each of the second semiconductor patterns extends in a third direction that substantially perpendicular to the top surface of the substrate, and wherein the semiconductor structures are arranged in a second direction with respect to each other, wherein the second direction is substantially perpendicular to the first direction in a plan view;
a common source region, a drain region, and a channel region formed in each of the semiconductor structures, the common source region and the drain region in each of the semiconductor structures being spaced apart from each other in the third direction, and the channel region being disposed between the common source region and the drain region in each of the semiconductor structures;
a channel body region formed in the second semiconductor patterns, wherein the channel body region is electrically connected to the channel region and extends in the first direction;
gate structures arranged between at least some of the second semiconductor patterns adjacent to each other in the second direction, wherein each of the gate structures serves as a shared gate electrode for two or more adjacent semiconductor patterns;
word line structures electrically connecting corresponding gate structures arranged in the first direction;
MTJ structures, each electrically connected to an upper portion of a corresponding one of the second semiconductor patterns; and
bit line structures, each bit line structure electrically connecting two MTJ structures adjacent to each other in the first direction to each other to form an MTJ structure group, each of the bit line structures extending in the second direction, and also electrically connecting a plurality of MTJ structure groups arranged in the second direction with respect to each other.

14. The device of claim 13 , where

Assignees

• Kim Eun-Jung
• Jang Se-Myeong
• Kim Dae-Ik
• Park Je-Min
• Hwang Yoo-Sang
• Samsung Electronics Co Ltd

Inventors

• Kim Eun-Jung
• Jang Se-Myeong
• Kim Dae-Ik
• Park Je-Min
• Hwang Yoo-Sang

Classifications

• H01L29/7827

  Electricity · mapped topic

• H01L27/228 Primary

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10B41/00 Primary

  Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates · CPC title