High voltage three-dimensional devices having dielectric liners

Patent metadata

Field	Value
Publication number	US-9570467-B2
Application number	US-201514641117-A
Country	US
Kind code	B2
Filing date	Mar 6, 2015
Priority date	Jun 28, 2012
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

First claim

What is claimed is:

1. A method of fabricating a semiconductor structure, the method comprising:
forming a plurality of fin active regions above a substrate;
forming a plurality of dummy gate structures above the plurality of fin active regions;
forming spacers adjacent the sidewalls of each of the plurality of dummy gate structures;
removing the dummy gate structures to form a plurality of gate locations defined by the spacers;
forming a first conformal dielectric layer to remain in a second of the plurality of gate locations but not in a first of the plurality of gate locations, wherein the first conformal dielectric layer is formed over a top surface of one or more of the plurality of fin active regions and along both sidewalls of each of the one or more of the plurality of fin active regions; and, subsequently,
forming a second conformal dielectric layer in the plurality of gate locations and on the first conformal dielectric layer; and, subsequently,
forming a low voltage device in the first of the plurality of gate locations and a high voltage device in the second of the plurality of gate locations, wherein the substrate is a bulk single crystalline silicon substrate, and the plurality of fin active regions is formed from and remain continuous with the bulk single crystalline silicon substrate in the low voltage device and in the high voltage device.

2. The method of claim 1 , wherein the first dielectric layer comprises silicon oxide, and the second dielectric layer comprises a high-k material.

3. The method of claim 1 , further comprising:
forming a first pair of contacts directly adjacent to the first spacers; and
forming a second pair of contacts directly adjacent to the second spacers.

4. The method of claim 1 , wherein forming the low and high voltage devices comprises forming metal gate electrodes.

5. The method of claim 1 , wherein forming the first and the second conformal dielectric layers comprises using atomic layer deposition (ALD) to form both layers.

Assignees

• Hafez Walid M
• Yeh Jeng-Ya D
• Tsai Curtis
• Park Joodong
• Jan Chia-Hong
• Bhimarasetti Gopinath
• Intel Corp

Inventors

• Hafez Walid M
• Yeh Jeng-Ya D
• Tsai Curtis
• Park Joodong
• Jan Chia-Hong
• Bhimarasetti Gopinath

Classifications

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/3458

  Monocrystalline · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/01332

  Making the insulator · CPC title