Tiled hybrid array and method of forming

Patent metadata

Field	Value
Publication number	US-9570428-B1
Application number	US-201614994917-A
Country	US
Kind code	B1
Filing date	Jan 13, 2016
Priority date	Aug 27, 2015
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A tiled array of hybrid assemblies and a method of forming such an array enables the assemblies to be placed close together. Each assembly comprises first and second dies, with the second die mounted on and interconnected with the first die. Each vertical edge of a second die which is to be located adjacent to a vertical edge of another second die in the tiled array is etched such that the etched edge is aligned with a vertical edge of the first die. Indium bumps are deposited on a baseplate where the hybrid assemblies are to be mounted, and the assemblies are mounted onto respective indium bumps using a hybridizing machine, enabling the assemblies to be placed close together, preferably ≦10 μm. The first and second dies may be, for example. a detector and a readout IC, or an array of LEDs and a read-in IC.

First claim

We claim:

1. A method of forming a tiled array of hybrid assemblies on a baseplate, comprising:
forming a plurality of hybrid assemblies, each of which comprises:
a first die; and
a second die mounted on and interconnected with said first die;

etching each vertical edge of said second dies which is to be located adjacent to a vertical edge of another second die in said tiled array such that said etched vertical edge is aligned with a vertical edge of said first die;
providing a baseplate on which said tiled array is to be mounted;
depositing a plurality of indium bumps on said baseplate where said hybrid assemblies are to be mounted; and
pressing said hybrid assemblies onto said indium bumps using a hybridizing machine.

2. The method of claim 1 , further comprising wicking epoxy into the gaps between said indium bumps.

3. The method of claim 1 , wherein adjacent edges of hybrid assemblies in said tiled array are ≦10 μm apart.

4. The method of claim 1 , wherein said etching comprises a dry plasma etch.

5. The method of claim 1 , wherein said etching comprises:
thinning the substrate of said second die; and
performing a wet etch on said thinned second die and said first die.

6. The method of claim 1 , wherein said first die comprises a readout IC (ROIC) and said second die comprises a detector comprising an array of detector pixels mounted on and interconnected with said ROIC.

7. The method of claim 6 , wherein said detector is a mercury cadmium telluride (MCT) detector on a CdZnTe substrate.

8. The method of claim 7 , wherein said etching comprises:
thinning said CdZnTe substrate;
depositing a photoresist on the surface of said second die opposite said first die; and
wet etching said surface of said second die such that any portion of said second die which extends beyond a vertical edge of said first die is substantially removed.

9. The method of claim 1 , wherein said first die comprises a read-in IC (RIIC) and said second die comprises an array of LEDs mounted to and interconnected with said RIIC.

10. The method of claim 1 , wherein said second die comprises an array of superlattice LEDs (SLEDs) on a gallium antimonide (GaSb) substrate.

11. The method of claim 9 , wherein said etching comprises:
depositing a layer on the surface of said first die opposite said second die which is resistant to a dry etchant; and
performing a dry etch such that said first die serves as an etching mask so that any portion of said second die which extends beyond a vertical edge of said first die is substantially removed.

12. The method of claim 1 , further comprising forming through-substrate vias (TSVs) through at least a portion of at least one of said hybrid assemblies.

13. The method of claim 1 , wherein said baseplate comprises copper tungsten (CuW).

14. The method of claim 1 , wherein said hybridizing machine is capable of placing hybrid assemblies on said baseplate with an accuracy of ±1 μm.

15. The method of claim 1 , wherein said hybridizing machine is a FC150 Automated Die/Flip Chip Bonder manufactured by Smart Equipment Technology.

16. A method of forming a tiled array of hybrid assemblies on a baseplate, comprising:
providing a plurality of first dies and a second wafer;
etching a plurality of steps, each with a vertical sidewall, into said second wafer;
dicing said second wafer into a plurality of second dies;
aligning the vertically etched edges of said second dies with the vertical edges of respective ones of said first dies;
bonding and electrically interconnecting said first dies to said second dies using indium bumps and epoxy to form a plurality of hybrid assemblies;
providing a baseplate on which said tiled array is to be mounted;
depositing a plurality of indium bumps on said baseplate where said hybrid assemblies are to be mounted; and
pressing said hybrid assemblies onto said indium bumps using a hybridizing machine.

17. The method of claim 16 , further comprising thinning said second wafer such that any portion of said second wafer which is overhanging said first die is removed.

18. The method of claim 17 , wherein thinning said second wafer comprises fly-cutting or mechanically lapping said second wafer.

19. A tiled hybrid array, comprising;
a baseplate;
a plurality of indium bumps on said baseplate;
a plurality of hybrid assemblies forming a tiled array mounted directly on said baseplate, at least a portion of each vertical edge of a hybrid assembly located adjacent to a vertical edge of another hybrid assembly being defined by an etch, said plurality of hybrid assemblies affixed to said baseplate via said indium bumps.

20. The tiled hybrid array of claim 19 , wherein said baseplate is a heat sink.

21. The tiled hybrid array of claim 19 , wherein said etched vertical edge portions are dry etched.

22. The tiled hybrid array of claim 19 , wherein said etched vertical edge portions are wet etched.

23. The tiled hybrid array of claim 19 , wherein each of said hybrid assemblies comprises:
a first die; and
a second die mounted on and interconnected with said first die, the vertical edges of said second die located adjacent to a vertical edge of another second die being said etched edges, said vertical edges etched to align with an edge of said first die.

24. The tiled hybrid array of claim 23 , wherein
said first die comprises a readout IC (ROIC); and
said second die comprises a detector comprising an array of pixels mounted on and interconnected with said ROIC;
the vertical edges of detectors located adjacent to a vertical edge of another detector etched such that each etched vertical edge is aligned with a vertical edge of said ROIC.

25. The tiled hybrid array of claim 24 , wherein said detector is a mercury cadmium telluride (MCT) detector.

26. The tiled hybrid array of claim 23 , wherein
said first die comprises a read-in IC (RIIC); and
said second die comprises an array of LEDs mounted to and interconnected with said RIIC;
the vertical edges of LED arrays located adjacent to a vertical edge of another LED array etched such that each etched vertical edge is aligned with a vertical edge of said RIIC.

27. The tiled hybrid array of claim 26 , wherein said second die comprises an array of superlattice LEDs (SLEDs) on a gallium antimonide (GaSb) substrate.

28. The tiled hybrid array of claim 19 , wherein adjacent edges of hybrid assemblies in said tiled array are ≦10 μm apart.

29. The tiled hybrid array of claim 19 , further comprising epoxy wicked into the gaps between said indium bumps.

30. The tiled hybrid array of claim 19 , wherein said baseplate comprises copper tungsten (CuW).

31. The tiled hybrid array of claim 19 , further comprising through-substrate vias (TSVs) through at least a portion of at least one of said hybrid assemblies.

Assignees

• Teledyne Scient & Imaging Llc

Inventors

• Zandian Majid
• Cooper Donald E
• Fischer Lisa L
• Gil Victor
• Sullivan Gerard

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H01L25/167 Primary

  Electricity · mapped topic

• H01L27/1469

  Electricity · mapped topic

• H01L33/0095

  Electricity · mapped topic

• H01L25/165

  Electricity · mapped topic