Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9570409-B2
Application number	US-201414495113-A
Country	US
Kind code	B2
Filing date	Sep 24, 2014
Priority date	Oct 11, 2013
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first interconnection line and a second interconnection line, the first interconnection line and the second interconnection line extending along a first axis on a first plane at a first level on a substrate such that the first interconnection line and the second interconnection line are in alignment along the first axis with a gap therebetween;
a direct contact plug extending in a direction perpendicular to the substrate towards an active region of the substrate;
a bypass interconnection line that extends on a second plane at a second level on the substrate, the second level being different from the first level such that the bypass interconnection line includes a region that is skewed across the gap an amount in a direction perpendicular to the first axis and parallel to the substrate to electrically isolate the bypass interconnect line from the direct contact plug; and
a plurality of contact plugs configured to connect the bypass interconnection line to the first interconnection line and the second interconnection line.

2. The semiconductor device of claim 1 , wherein the first plane and the second plane are parallel to the substrate.

3. The semiconductor device of claim 1 , wherein the plurality of contact plugs comprises:
a first contact plug connected between the first interconnection line and the bypass interconnection line; and
a second contact plug connected between the second interconnection line and the bypass interconnection line.

4. The semiconductor device of claim 3 , wherein each of the first and second contact plugs extends in a direction perpendicular to the substrate.

5. The semiconductor device of claim 1 ,
wherein
the bypass interconnection line is spaced apart from the direct contact plug.

6. The semiconductor device of claim 1 , wherein a vertical distance from the substrate to the second plane is smaller than a vertical distance from the substrate to the first plane.

7. The semiconductor device of claim 1 , wherein a vertical distance from the substrate to the second plane is larger than a vertical distance from the substrate to the first plane.

8. The semiconductor device of claim 1 , wherein each of the first and second interconnection lines include a portion which vertically overlaps with the bypass interconnection line.

9. The semiconductor device of claim 1 , wherein the bypass interconnection line is configured to protect the semiconductor device from a short-circuit.

10. The semiconductor device of claim 1 , wherein the first interconnection line and the second interconnection line extend along a first axis in opposite directions with the gap therebetween, and the semiconductor device further comprises:
a fourth interconnection line on the first plane adjacent to the first interconnection line and the second interconnection line, the fourth interconnection line including a contact region, the contact region extending in a direction perpendicular to the first axis towards the first interconnection line and the second interconnection, the contact region connected to the direct contact plug, wherein
the bypass interconnection line is spaced apart from the direct contact plug and the fourth interconnection line.

11. A semiconductor device comprising:
a first interconnection line and a second interconnection line, the first interconnection line extending in a direction opposite the second interconnection line on a first plane at a first level on a substrate;
a bypass interconnection line that extends on a second plane at a second level on the substrate, the second level being different from the first level;
a plurality of contact plugs configured to connect the bypass interconnection line to the first interconnection line and the second interconnection line; and
a third interconnection line extending in the first plane, the third interconnection line including a portion which vertically overlaps with the bypass interconnection line and extends parallel to at least one of the first interconnection line and the second interconnection line.

12. A semiconductor device comprising:
a substrate including a cell array area and a core area disposed around the cell array area, the cell array area including a plurality of memory cells;
a pair of conductive lines in the cell array area;
a plurality of buried contacts between the pair of conductive lines, the plurality of buried contacts connected to an active region of the substrate;
a plurality of conductive landing pads extending in the cell array area from an upper surface of the plurality of buried contacts to a top of one of the pair of the conductive lines;
first and second interconnection lines extending along a first axis in the core area apart from each other on a first plane such that the first and second interconnection lines are at a first level higher than the upper surfaces of the plurality of conductive landing pads and the first and second interconnection lines are in alignment along the first axis with a gap therebetween;
a direct contact plug extending in a direction perpendicular to the substrate towards the active region of the substrate;
a bypass interconnection line extending in the core area on a second plane such that the bypass interconnection line is at a second level lower than the upper surfaces of the plurality of conductive landing pads, the bypass interconnection line including a region that is skewed across the gap an amount in a direction perpendicular to the first axis and parallel to the substrate such that the bypass interconnect line is electrically isolated from the direct contact plug; and
a plurality of contact plugs connected between the bypass interconnection line and the first and second interconnection lines.

13. The semiconductor device of claim 12 , wherein the plurality of contact plugs include a same material as the plurality of landing pads.

14. The semiconductor device of claim 12 , wherein the first interconnection line and the second interconnection line extend in different directions.

15. The semiconductor device of claim 12 , wherein the first interconnection line extends parallel to the second interconnection line.

16. A semiconductor device comprising:
a substrate having a first layer and a second layer thereon;
first and second interconnect lines on the first layer of the semiconductor device, the first and second interconnect lines extending along a first axis in opposite directions and having a gap therebetween along the first axis;
a non-linear interconnect line on the first layer, the non-linear interconnect line running parallel to the first and second interconnect lines and having a contact region, the contact region making the interconnect line non-linear by extending in a direction perpendicular to the first axis towards the first and second interconnect lines such that the contact region is wider than a rest of the non-linear interconnect line;
a direct contact plug extending in a direction perpendicular to the substrate from the contact region to an active region of the substrate;
a bypass interconnect line on the second layer of the semiconductor device, the bypass interconnection line including a region extending an amount in the direction perpendicular to the first axis and parallel to the substrate such that the bypass interconnect line is electrically isolated from the direct contact plug; and
first and second contact plugs respectively connecting the first and second interconnect lines to the bypass interconnect line such that the first and second interconnect lines are elec

Assignees

• Park Je-Min
• Kim Dae-Ik
• Samsung Electronics Co Ltd

Inventors

• Park Je-Min
• Kim Dae-Ik

Classifications

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C8/10

  Decoders · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title