Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application

Patent metadata

Field	Value
Publication number	US-9570404-B2
Application number	US-201414242851-A
Country	US
Kind code	B2
Filing date	Apr 1, 2014
Priority date	Apr 28, 2011
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

First claim

We claim:

1. A method for manufacturing a semiconductor power device comprising a source metal and a gate metal electrically connected to a source and gate of the semiconductor power device respectively, wherein the method comprising:
opening a plurality of trenches in a substrate and filling said trench with a conductive gate material; and
applying a mask for carrying out a time etch for etching back said gate material from selected trenches, each adjacent to active transistor cells, thus leaving a bottom portion in said selected trenches and leaving the trenches covered by the mask still filled with the gate conductive material;
covering the bottom portion in said selected trenches with a shielding insulation to form a bottom shielding electrode;
designating some of the trenches still filled with the conductive gate material as source contact trenches for contacting the source metal and reminder of the trenches filled with the conductive gate material as gate contact trenches for contacting the gate metal; and
electrically contacting a first predetermined set of the bottom shielding electrodes to at least one of the source contact trench and a second predetermined set of the bottom shielding electrodes to at least one of the gate contact trenches.

2. The method of claim 1 further comprising:
the step of designating some of the trenches as the gate contact trenches further comprising a step of designating some of the trenches in a termination area away from the active cells as the gate contact trenches for contacting the gate metal covering over the termination area.

3. The method of claim 1 further comprising:
the step of designating some of the trenches as the source contact trenches further comprising a step of designating some of the trenches in an active cell area adjacent to the active cells as the source contact trenches for contacting the source metal covering over the active cell area.

4. The method of claim 1 further comprising:
the step of electrically contacting respectively the first predetermined set and the second predetermined set of the bottom shielding electrodes to the source contact trenches and the gate metal respectively further comprising a step of configuring the second predetermined set about 1% to 50% of the first predetermined set of the bottom shielding electrodes.

5. The method of claim 1 further comprising:
forming an insulation layer for covering a top surface of said semiconductor power device and opening a plurality of source contact openings on top of said remainder portion of said trench to form source contact to direct contact said gate material in said remainder portion of said trench for electrically connecting to said bottom shielding electrode.

6. The method of claim 1 further comprising:
forming an insulation layer for covering a top surface of said semiconductor power device and opening at least a gate contact opening for providing a gate pad to electrically connecting to said gate material in said trenched gate in said selected portion of said trench.

7. The method of claim 1 wherein:
the step of opening the plurality of trenches further comprising a step of opening a plurality gate runner trenches extended from gate trenches in an active area near the active transistor cells to the gate-contacting trenches disposed in an termination area; and
the step of electrically contacting the second predetermined set of bottom shielding electrodes to the gate-contacting trenches further comprising a step of filling the gate runner trenches with the conductive gate material for electrically contacting the second predetermined set of bottom shielding electrodes to the gate-contacting trenches through the gate runner trenches.

Assignees

• Pang Ji
• Ng Daniel
• Bhalla Anup
• Wang Xiaobin
• Alpha & Omega Semiconductor

Inventors

• Pang Ji
• Ng Daniel
• Bhalla Anup
• Wang Xiaobin

Classifications

• H10W42/20 Primary

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H01L29/7823

  Electricity · mapped topic

• H01L29/7825

  Electricity · mapped topic