Template matching for resilience and security characteristics of sub-component chip designs

Patent metadata

Field	Value
Publication number	US-9569582-B2
Application number	US-201414146770-A
Country	US
Kind code	B2
Filing date	Jan 3, 2014
Priority date	Jan 3, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A mechanism is provided for validating overall resilience and security characteristics of a sub-component chip design. For each instance of a resiliency template identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections, a determination is made as to whether an output of the design netlist where an error signal is output interconnects to the one or more identified resiliency sections of the design netlist. Responsive to the one or more identified resiliency sections interconnecting to the output of the design netlist where the error signal is output, one or more identified resiliency sections are marked as being protected by the error signal. An identification of the one or more identified resiliency sections and an identification of the error signal protecting the one or more identified resiliency sections are output to a design team.

First claim

What is claimed is:

1. A method, in a data processing system comprising a processor and a memory coupled to the processor, the memory comprising instructions executed by the processor to cause the processor to validate overall resilience and security characteristics of a sub-component chip design, the method comprising:
for each instance of a resiliency template in a set of resiliency templates identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections of the design netlist, determining, by the processor, whether an output of the design netlist, where an error signal is output, interconnects to the one or more identified resiliency sections of the design netlist, wherein each resiliency template in the set of resiliency templates is a known circuit design pattern used to check for transient or permanent errors in a chip design;
responsive to the one or more identified resiliency sections of the design netlist interconnecting to the output of the design netlist where the error signal is output, marking, by the processor, the one or more identified resiliency sections of the design netlist as being protected by the error signal; and
outputting, by the processor, an identification of the one or more identified resiliency sections of the design netlist and an identification of the error signal protecting the one or more identified resiliency sections of the design netlist to a design team of a larger chip design where the sub-component chip design is to be integrated.

2. The method of claim 1 , further comprising:
repeating, by the processor, the determination of whether the output, associated with the error signal, interconnects to the one or more identified resiliency sections of the design netlist for each error signal in a plurality of error signals; and
responsive to the one or more identified resiliency sections of the design netlist interconnecting to the output of the design netlist of more than one error signal in the plurality of error signals, outputting, by the processor, each identification of the one or more identified resiliency sections of the design netlist and each identification of the error signal in the set of error signals protecting the one or more identified resiliency sections of the design netlist to the design team of the larger chip design where the sub-component chip design is to be integrated.

3. The method of claim 1 , wherein determining whether the output of the design netlist, where the error signal is output, interconnects to the one or more identified resiliency sections of the design netlist is performed in a breadth-first search (BFS) manner.

4. The method of claim 1 , wherein the appearance of the resiliency template in the sub-component chip design is determined by the method comprising:
searching, by the processor, the design netlist for an appearance of each resiliency template in the set of resiliency templates; and
responsive to identifying an appearance of the resiliency template in the design netlist, recording, by the processor, an identification of the resiliency template and the inputs and outputs of the design netlist associated with the appearance of resiliency template in the design netlist in a resiliency input/output data structure.

5. The method of claim 1 , wherein the error signal is at least one of parity, error-correcting code, syndrome calculation, state checking, orthogonality, state bit checking, or residue checking.

6. The method of claim 1 , further comprising:
searching, by the processor, the design netlist for an appearance of each security template in a set of security templates;
responsive to identifying an appearance of the security template in the design netlist thereby forming an identified security section of the design netlist, recording, by the processor, an identification of the security template and the inputs and outputs of the design netlist associated with the appearance of security template in the design netlist in a security input/output data structure; and
outputting, by the processor, an identification of the identified security section of the design netlist recorded in the security input/output data structure to the design team of the larger chip design where the sub-component chip design is to be integrated.

7. The method of claim 1 , wherein the resiliency template is a known structure of interconnections, a known structure of firmware blocks or hardware/firmware blocks, a certain configuration bits of test structures and matching patterns, or a configuration bits in processor with patterns of hardware.

8. A computer program product comprising a non-transitory computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:
for each instance of a resiliency template in a set of resiliency templates identified as appearing in a design netlist of the sub-component chip design thereby forming one or more identified resiliency sections of the design netlist, determine whether an output of the design netlist where an error signal is output, interconnects to the one or more identified resiliency sections of the design netlist, wherein each resiliency template in the set of resiliency templates is a known circuit design pattern used to check for transient or permanent errors in a chip design;
responsive to the one or more identified resiliency sections of the design netlist interconnecting to the output of the design netlist where the error signal is output, mark the one or more identified resiliency sections of the design netlist as being protected by the error signal; and
output an identification of the one or more identified resiliency sections of the design netlist and an identification of the error signal protecting the one or more identified resiliency sections of the design netlist to a design team of a larger chip design where the sub-component chip design is to be integrated.

9. The computer program product of claim 8 , wherein the computer readable program further causes the computing device to:
repeat the computer readable program to determine whether the output, associated with the error signal, interconnects to the one or more identified resiliency sections of the design netlist for each error signal in a plurality of error signals; and
responsive to the one or more identified resiliency sections of the design netlist interconnecting to the output of the design netlist of more than one error signal in the plurality of error signals, output each identification of the one or more identified resiliency sections of the design netlist and each identification of the error signal in the set of error signals protecting the one or more identified resiliency sections of the design netlist to the design team of the larger chip design where the sub-component chip design is to be integrated.

10. The computer program product of claim 8 , wherein determining whether the output of the design netlist where the error signal is output interconnects to the one or more identified resiliency sections of the design netlist is performed in a breadth-first search (BFS) manner.

11. The computer program product of claim 8 , wherein the appearance of the resiliency template in the sub-component chip design is determined by the computer readable program further causing the computing device to:
search the design netlist for an appearance of each resiliency template in the set of resiliency templates; and
responsive to identifying an appearance of the resiliency template in the design netlist, record an identification of the resiliency

Assignees

• IBM

Inventors

• Arbel Eli
• Bose Pradip
• Kudva Prabhakar
• Moran Shiri
• Muller K Paul

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5081 Primary

  Physics · mapped topic

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/30

  Circuit design · CPC title