Memory device, memory system, and operating method of memory system

Patent metadata

Field	Value
Publication number	US-9569371-B2
Application number	US-201514626989-A
Country	US
Kind code	B2
Filing date	Feb 20, 2015
Priority date	Jun 13, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A memory device, a memory system, and an operating method of the memory system is provided. The operating method includes operations of transmitting an authentication request to a memory device using a memory controller; converting the authentication request to a first address using the memory device; processing authentication data that corresponds to the first address and indicates a physical characteristic of the memory device and transmitting the authentication data as an authentication response to the authentication request to the memory controller using the memory device; and verifying whether the authentication response received from the memory device is an authentication response to the authentication request using the memory controller.

First claim

What is claimed is:

1. An operating method of a memory system, the operating method comprising:
transmitting an authentication request to a memory device using a memory controller;
converting the authentication request to a first address corresponding to a data area using the memory device, wherein the authentication request comprises request to access the data area for processing authentication data that indicate a physical characteristic of the memory device;
processing the authentication data that corresponds to the first address and transmitting the authentication data as an authentication response to the authentication request to the memory controller using the memory device;
verifying whether the authentication response received from the memory device is an authentication response to the authentication request using the memory controller; and
when it is verified that the authentication response is the authentication response to the authentication request, permitting normal access to the memory device, wherein the permitting of the normal access comprises encrypting a second address for the normal access to the memory device using the memory controller, decrypting the encrypted second address using the memory controller, and performing a normal operation on the decrypted second address using the memory device.

2. The operating method of claim 1 , wherein the verifying comprises:
converting the authentication request to the first address using the memory controller; and
comparing set data that is set for the first address with the authentication data that is extracted from the authentication response transmitted from the memory device using the memory controller.

3. The operating method of claim 2 , wherein each of the memory controller and the memory device converts the authentication request to the first address using an address generator that equally generates the first address with respect to the authentication request.

4. The operating method of claim 1 , wherein the verifying comprises:
searching for the first address that is mapped to the authentication request using the memory controller; and
comparing set data that is set for the first address with the authentication data that is extracted from the authentication response transmitted from the memory device using the memory controller.

5. The operating method of claim 1 , further comprising, between the processing and the transmitting, encrypting the authentication data and generating the encrypted authentication data as the authentication response.

6. The operating method of claim 1 , further comprising:
exchanging a Number Used Once (nonce) between the memory controller and the memory device; and
setting the authentication request that corresponds to the nonce using the memory controller.

7. The operating method of claim 1 , wherein each of the encrypting and the decrypting is performed using the authentication response as a secret key.

8. The operating method of claim 1 , wherein the memory device comprises a NAND flash memory device.

9. The operating method of claim 1 , wherein the memory system comprises a solid state drive (SSD).

10. The operating method of claim 1 , wherein the memory device converts the authentication request to the first address corresponding to size to the authentication data.

11. An operating method of a memory system, the operating method comprising:
exchanging a Number Used Once (nonce) between a memory controller and a memory device;
generating a challenge using the nonce by each of the memory controller and the memory device;
converting the challenge to a first address corresponding to a data area using the memory device, wherein the authentication request comprises request to access the data area for processing authentication data that indicate a physical characteristic of the memory device;
reading the authentication data that corresponds to the first address using the memory device;
transmitting a response corresponding to the challenge to the memory device using the memory controller;
comparing the authentication data with the response received from the memory controller and verifying whether the response received from the memory controller is a response that forms a challenge-response pair with the challenge using the memory device; and
when the response received from the memory controller is the response that forms the challenge-response pair with the challenge, permitting normal access to the memory device, wherein the permitting of normal access comprises encrypting a second address for the normal access to the memory device using the memory controller and using the response as a secret key, decrypting the encrypted second address using the response as a secret key and using the memory device, and performing a normal operation on the decrypted second address using the memory device.

12. The operating method of claim 11 , wherein the transmitting comprises: searching for the response that is mapped to the challenge using the memory controller; and transmitting the response to the memory device.

13. A memory system, comprising:
a memory controller configured to transmit an authentication request;
a memory device configured to:
convert the authentication request to a first address corresponding to a data area using the memory device, wherein the authentication request comprises request to access the data area for processing authentication data that indicate a physical characteristic of the memory device,
process the authentication data, the authentication data corresponding to the first address, and
transmit the authentication data as an authentication response to the authentication request to the memory controller, wherein the memory controller is configured to generate set data setting for a first address converted from the authentication request, extract the authentication data from the authentication response transmitted from the memory device, and verify whether the authentication response received from the memory device is an authentication response to the authentication request by comparing the set data with the authentication data;
the memory controller is further configured to encrypt a second address for normal access to the memory device using the authentication response as a secret key, when it is verified that the authentication response is the authentication response to the authentication request; and
the memory device is further configured to decrypt the encrypted second address using the authentication response as the secret key and perform the normal operation on the decrypted second address.

14. The memory system of claim 13 , wherein each of the memory controller and the memory device comprise an address generator that equally generates the first address with respect to the authentication request.

15. The memory system of claim 13 , wherein the memory system comprises a solid state drive (SSD).

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Seong-Hyeog
• Kong Jun-Jin
• Son Hong-Rak
• Yoon Pil-Sang
• Seol Chang-Kyu

Classifications

• G06F12/1408 Primary

  by using cryptography (for digital transmission H04L9/00) · CPC title

• G06F2212/1052

  Security improvement · CPC title

• H04L9/3278 Primary

  using physically unclonable functions [PUF] · CPC title