System and method to provide non-coherent access to a coherent memory system

Patent metadata

Field	Value
Publication number	US-9569366-B2
Application number	US-201414466384-A
Country	US
Kind code	B2
Filing date	Aug 22, 2014
Priority date	Oct 25, 2011
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

First claim

What is claimed is:

1. A system comprising:
a memory;
a memory controller providing a cache access path to the memory and a bypass-cache access path to the memory, the memory controller receiving requests to access finite automata (FA) data at the memory on the bypass-cache access path and receiving requests to access non-FA data at the memory on the cache access path, the finite automata (FA) data including non-deterministic finite automata (NFA) data.

2. The system of claim 1 wherein the memory controller receives requests to access FA data and non-FA data at the memory on the cache access path.

3. The system of claim 1 wherein the non-FA data comprises packet data.

4. The system of claim 1 wherein the memory stores FA data and non-FA data.

5. The system of claim 1 wherein the memory controller reads the requested FA data or non-FA data.

6. The system of claim 1 wherein the memory controller receives the requests to access FA data from a co-processor.

7. The system of claim 6 wherein the co-processor includes at least one of a deterministic automata processing unit and a nondeterministic automata processing unit.

8. The system of claim 6 wherein the co-processor is configured to stop sending access requests to the memory controller to stop the access of selected FA data from the memory when the selected FA data is being written to the memory on the cache access path.

9. The system of claim 1 wherein the memory controller receives requests to access FA data and non-FA data from a cache controller.

10. The system of claim 1 wherein the memory controller is configured to arbitrate among requests from the cache access path and the bypass-cache access path using at least one of fixed priority arbitration, round-robin arbitration, and weighted round-robin arbitration.

11. The system of claim 1 wherein the FA data is non-sequentially addressed data and the non-FA data is sequentially addressed data.

12. The system of claim 1 further comprising a cache, the cache associated with the memory and wherein the cache access path provides access to the memory through the cache and the bypass-cache access path provides access to the memory by bypassing the cache.

13. The system of claim 12 wherein the cache is coherently associated with the memory.

14. A method comprising:
receiving one or more requests at a memory controller to access finite automata (FA) data at a memory on a bypass-cache access path, the finite automata (FA) data including non-deterministic finite automata (NFA) data;
receiving one or more requests at the memory controller to access non-FA data at the memory through a cache access path;
arbitrating, in the memory controller, among the requests using at least one of fixed priority arbitration, round-robin arbitration, and weighted round-robin arbitration.

15. The method of claim 14 further comprising receiving one or more requests at the memory controller to access FA data and non-FA data at the memory through a cache access path.

16. The method of claim 14 further comprising reading from the memory the requested FA data or non-FA data.

17. The method of claim 14 wherein the non-FA data comprises packet data.

18. The method of claim 14 wherein the memory controller receives the requests to access FA data from a co-processor.

19. The method of claim 18 wherein the co-processor includes at least one of a deterministic automata processing unit and a nondeterministic automata processing unit.

20. The method of claim 14 wherein the memory controller receives the requests to access non-FA data and FA data from a cache controller through the cache access path.

21. The method of claim 14 further comprising stopping the access of selected FA data from the memory while the selected FA data is being written to the memory on the cache access path.

22. The method of claim 14 wherein the memory stores FA data and non-FA data.

23. The method of claim 14 wherein the FA data is non-sequentially addressed data and the non-FA data is sequentially addressed data.

24. The method of claim 14 wherein a cache is associated with the memory and the cache access path provides access to the memory through the cache and the bypass-cache access path provides access to the memory by bypassing the cache.

25. The method of claim 24 wherein the cache is coherently associated with the memory.

Assignees

• Cavium Inc

Inventors

• Pangborn Jeffrey A
• Bouchard Gregg A
• Goyal Rajan
• Kessler Richard E
• Maheshwari Aseem

Classifications

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F12/0888 Primary

  using selective caching, e.g. bypass · CPC title