Programmable ordering and prefetch

Patent metadata

Field	Value
Publication number	US-9569362-B2
Application number	US-201414540379-A
Country	US
Kind code	B2
Filing date	Nov 13, 2014
Priority date	Nov 13, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

An input/output bridge controls access to a memory by a number of devices. The bridge enforces ordering of access requests according to a register storing an order configuration, which can be programmed to accommodate a given application. When suspending an access request as a result of enforcing an order configuration, the bridge may also cause a prefetch at the memory for the suspended access request. Subsequently, following the completion of a previous access request meeting the order configuration, the suspended access request is released. Due to the prefetch, an access operation can be completed with minimal delay.

First claim

What is claimed is:

1. A circuit for controlling access to a memory, comprising:
a register storing an order configuration, the order configuration indicating rules for ordering access requests;
a request buffer configured to receive first and second access requests;
prefetch buffer configured to receive the first and second access requests in parallel with the request buffer; and
a control circuit configured to:
forward the first access request to a memory;
monitor the completion status of the first access request;
selectively forward or suspend the second access request based on the order configuration and the completion status of the first access request; and
in response to suspending the second access request, forward a prefetch command to the memory and forward a third request from the prefetch buffer to the memory.

2. The circuit of claim 1 , wherein the order configuration indicates whether to enforce ordering among at least two sequential access requests based on a respective type of each of the at least two sequential access requests.

3. The circuit of claim 2 , wherein the respective type includes at least one of a memory write request and a memory read request.

4. The circuit of claim 1 , wherein the order configuration includes a Peripheral Component Interconnect (PCI) order configuration.

5. The circuit of claim 1 , wherein the control circuit selectively forwards the first and second access requests via a PCI memory bus.

6. The circuit of claim 5 , wherein the order configuration deviates from a PCI order configuration.

7. The circuit of claim 1 , wherein the first and second access requests include at least one of a memory write request and a memory read request.

8. The circuit of claim 1 , wherein the prefetch command indicates a block of memory to be stored to a level 2 cache (L2C), the block of memory including an address of the memory indicated by the second access request.

9. The circuit of claim 1 , wherein the control circuit, in response to detecting that the first and second access requests match at least one of the rules for ordering access requests, suspends the second access request until detecting that the first access request is completed.

10. The circuit of claim 1 , wherein the control circuit is further configured to select access requests from the request buffer and the prefetch buffer.

11. The circuit of claim 1 , further comprising at least one counter configured to maintain a count of pending access requests, the control circuit selectively forwarding or suspending the second access request based on the count in addition to the order configuration and the completion status of the first access request.

12. A method of accessing a memory, comprising:
forwarding a first access request and a second access request to a memory;
storing the first and second access requests to a request buffer and a prefetch buffer in parallel;
monitoring the completion status of the first access request;
selectively forwarding or suspending the second access request based on an order configuration and the completion status of the first access request, the order configuration indicating rules for ordering access requests; and
in response to suspending the second access request, forwarding a prefetch command to the memory and forwarding a third request from the prefetch buffer to the memory.

13. The method of claim 12 , wherein the order configuration indicates whether to enforce ordering among at least two sequential access requests based on a respective type of each of the at least two sequential access requests.

14. The method of claim 13 , wherein the respective type includes at least one of a memory write request and a memory read request.

15. The method of claim 12 , wherein the order configuration includes a Peripheral Component Interconnect (PCI) order configuration.

16. The method of claim 12 , further comprising selectively forwarding the first and second access requests via a PCI memory bus.

17. The method of claim 16 , wherein the order configuration deviates from a PCI order configuration.

18. The method of claim 12 , wherein the first and second access requests include at least one of a memory write request and a memory read request.

19. The method of claim 12 , wherein the prefetch command indicates a block of memory to be stored to a level 2 cache (L2C), the block of memory including an address of the memory indicated by the second access request.

20. The method of claim 12 , further comprising, in response to detecting that the first and second access requests match at least one of the rules for ordering access requests, suspending the second access request until detecting that the first access request is completed.

21. The method of claim 12 , further comprising selecting access requests from the request buffer and the prefetch buffer.

22. The method of claim 12 , further comprising maintaining a count of pending access requests, the selectively forwarding or suspending the second access request being based on the count in addition to the order configuration and the completion status of the first access request.

Assignees

• Cavium Inc

Inventors

• Sanzone Robert A
• Snyder Ii Wilson P
• Kessler Richard E

Classifications

• G06F12/084

  with a shared cache · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F2212/6022

  Using a prefetch buffer or dedicated prefetch cache · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title