Recovery of multi-page failures in non-volatile memory system

Patent metadata

Field	Value
Publication number	US-9569306-B1
Application number	US-201514975237-A
Country	US
Kind code	B1
Filing date	Dec 18, 2015
Priority date	Dec 18, 2015
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A data storage system includes a controller and a non-volatile memory array having a plurality of blocks each including a plurality of physical pages. The controller maintains a logical-to-physical translation (LPT) data structure that maps logical addresses to physical addresses and implements a first data protection scheme that stripes write data over the plurality of physical blocks. In response to a read request requesting data from a target page stripe, the controller detecting errors in multiple physical pages of the target page stripe. In responsive to detecting errors in multiple physical pages of the target page stripe, the controller scans the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggers recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes transmitting the set of logical addresses to the higher level controller.

First claim

What is claimed is:

1. A method in a data storage system including a non-volatile memory array controlled by a controller, wherein the non-volatile memory array includes a plurality of blocks each including a plurality of physical pages, the method comprising:
the controller maintaining a logical-to-physical translation (LPT) data structure that maps logical addresses to physical addresses in the non-volatile memory array;
the controller implementing a first data protection scheme that stripes write data over the plurality of physical blocks to form a plurality of page stripes;
in response to a read request requesting data from a target page stripe among the plurality of page stripes, the controller detecting errors in data read from multiple physical pages storing data of the target page stripe, wherein the errors are not correctable by the controller utilizing the first data protection scheme; and
in response to detecting errors that are not correctable by the controller utilizing the first data protection scheme in data read from multiple physical pages of the target page stripe, the controller scanning the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggering recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes the controller transmitting the set of logical addresses to the higher level controller.

2. The method of claim 1 , and further comprising:
the controller determining whether the higher level controller has completed reconstruction of the target page stripe; and
in response to determining that the higher level controller has completed reconstruction of the target page stripe, the controller relocating contents of a block stripe that included the target page stripe and multiple other page stripes within the non-volatile memory array.

3. The method of claim 1 , wherein:
the controller controls a first memory device;
the first data protection scheme comprises a parity-based data protection scheme; and
the second data protection scheme comprises a redundant array of independent disks (RAID) data protection scheme over a plurality of memory devices including the first memory device.

4. The method of claim 1 , and further comprising:
the controller detecting errors in data read from the multiple physical pages of the target page stripe utilizing a third data protection scheme that employs error correcting codes (ECC).

5. The method of claim 1 , and further comprising the controller transmitting a read error to the higher level controller in response to the read request being a host read request.

6. The method of claim 1 , wherein:
the set of logical addresses are mapped to only a subset of the pages of the target page stripe.

7. The method of claim 1 , and further comprising:
in response to detecting one or more errors in a single data page of the target page stripe, the controller recovering contents of the target page utilizing the first data protection scheme.

8. The method of claim 1 , wherein the controller performs the transmitting of the set of logical addresses to the higher level controller in response to receipt of a request from the higher level controller.

9. A data storage system, comprising:
a controller configured to be coupled to a non-volatile memory array including a plurality of blocks each including multiple physical pages and to a memory that includes a logical-to-physical translation (LPT) data structure that maps logical addresses to physical addresses in the non-volatile memory array, wherein the controller is configured to implement a first data protection scheme that stripes write data over the plurality of physical blocks to form a plurality of page stripes, wherein the controller is configured, responsive to a read request requesting data from a target page stripe among the plurality of page stripes, to detect errors in data read from multiple physical pages storing data of the target page stripe and, responsive to detecting errors that are not correctable by the controller utilizing the first data protection scheme in data read from multiple physical pages of the target page stripe, to scan the LPT data structure to identify a set of logical addresses mapped to the target page stripe and to trigger recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein the controller transmits the set of logical addresses to the higher level controller.

10. The data storage system of claim 9 , wherein the controller is further configured to determine whether the higher level controller has completed reconstruction of the target page stripe and, responsive to determining that the higher level controller has completed reconstruction of the target page stripe, to relocate contents of a block stripe that included the target page stripe and multiple other page stripes within the non-volatile memory array.

11. The data storage system of claim 9 , wherein:
the controller controls a first memory device;
the first data protection scheme comprises a parity-based data protection scheme; and
the second data protection scheme comprises a redundant array of independent disks (RAID) data protection scheme over a plurality of memory devices including the first memory device.

12. The data storage system of claim 9 , wherein the controller is further configured to detect errors in data read from multiple physical pages of the target page stripe utilizing a third data protection scheme that employs error correcting codes (ECC).

13. The data storage system of claim 9 , wherein the controller is configured to transmit a read error to the higher level controller in response to the read request being a host read request.

14. The data storage system of claim 9 , wherein:
the set of logical addresses are mapped to only a subset of the pages of the target page stripe.

15. The data storage system of claim 9 , wherein the controller is configured, responsive to detecting one or more errors in a single data page of the target page stripe, to recover contents of the target page utilizing the first data protection scheme.

16. The data storage system of claim 9 , wherein the controller is configured to transmit the set of logical addresses to the higher level controller in response to receipt of a request from the higher level controller.

17. The data storage system of claim 9 , and further comprising the non-volatile memory array coupled to the controller.

18. A computer program product, the computer program product comprising a computer readable storage device having program instructions embodied therewith, the program instructions executable by a controller for a non-volatile memory array including a plurality of blocks each including a plurality of physical pages, to cause the controller to perform:
the controller maintaining a logical-to-physical translation (LPT) data structure that maps logical addresses to physical addresses in the non-volatile memory array;
the controller implementing a first data protection scheme that stripes write data over the plurality of physical blocks to form a plurality of page stripes;
in response to a read request requesting data from a target page stripe among the plurality of page stripes, the controller detecting errors in data read from multiple physical pages storing data of the target page stripe, wherein the errors are not correctable by the controller utilizing the first data protection scheme; and

Assignees

• IBM

Inventors

• Camp Charles J
• Fisher Timothy J
• Fry Aaron D
• Ioannou Nikolas
• Parnell Thomas
• Pletka Roman A
• Tomic Sasa

Classifications

• G06F12/10

  Address translation · CPC title

• G06F2212/202

  Non-volatile memory · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title