Asymmetric performance multicore architecture with same instruction set architecture

Patent metadata

Field	Value
Publication number	US-9569278-B2
Application number	US-201113335257-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.

First claim

What is claimed is:

1. A multi-core processor comprising:
a first plurality of cores and a second plurality of cores that support a same instruction set, wherein the second plurality of cores consume less power, for a same applied operating frequency and supply voltage, than the first plurality of cores; and
power management hardware to, from an initial state where the first plurality of cores and the second plurality of cores are enabled, disable an additional core of the first plurality of cores for each continued drop in demand below a next lower threshold without disabling any of the second plurality of cores until the first plurality of cores is disabled, disable an additional core of the second plurality of cores for each continued drop in demand below a next lower threshold until one core of the second plurality of cores remains enabled, and lower at least one of an operating frequency and a supply voltage of the one core of the second plurality of cores as demand drops below a next lower threshold.

2. The multi-core processor of claim 1 wherein the second plurality of cores include logic gates that have narrower logic gate driver transistors than a corresponding logic gate of the first plurality of cores.

3. The multi-core processor of claim 1 wherein the second plurality of cores comprise logic gates that consume less power than a corresponding logic gate of the first plurality of cores.

4. The multi-core processor of claim 1 wherein the second plurality of cores each have a maximum operating frequency that is less than a maximum operating frequency of the first plurality of cores.

5. The multi-core processor of claim 1 further comprising a switch fabric between the first plurality of cores, the second plurality of cores, and a system memory interface.

6. A method comprising:
operating a multi-core processor such that a first plurality of cores and a second plurality of cores support respective software routines with a same instruction set, the first plurality of cores being higher performance and consuming more power than the second plurality of cores under a same applied supply voltage and operating frequency; and
disabling with power management hardware, from an initial state where the first plurality of cores and the second plurality of cores are enabled, an additional core of the first plurality of cores for each continued drop in demand below a next lower threshold without disabling any of the second plurality of cores until the first plurality of cores is disabled, disabling an additional core of the second plurality of cores for each continued drop in demand below a next lower threshold until one core of the second plurality of cores remains enabled, and lowering at least one of an operating frequency and a supply voltage of the one core of the second plurality of cores as demand drops below a next lower threshold.

7. The method of claim 6 wherein the operating of the first plurality of cores includes driving load lines with wider transistor widths than corresponding transistor widths in said second plurality of cores.

8. The method of claim 6 further comprising lowering at least one of a supply voltage and an operating frequency of said one core in response to lower demand being offered to said multi-core processor.

9. The method of claim 8 further comprising raising at least one of a supply voltage and an operating frequency of said one core in response to higher demand being offered to said multi-core processor.

10. The method of claim 6 further comprising:
raising at least one of a supply voltage and an operating frequency of said one core in response to higher demand being offered to said multi-core processor.

11. A non-transitory machine readable medium containing program code that when processed by a machine causes a method to be performed, the method comprising:
operating a multi-core processor such that a first plurality of cores and a second plurality of cores support respective software routines with a same instruction set, the first plurality of cores being higher performance and consuming more power than a second plurality of cores under a same applied supply voltage and operating frequency; and
disabling with power management hardware, from an initial state where the first plurality of cores and the second plurality of cores are enabled, an additional core of the first plurality of cores for each continued drop in demand below a next lower threshold without disabling any of the second plurality of cores until the first plurality of cores is disabled, disabling an additional core of the second plurality of cores for each continued drop in demand below a next lower threshold until one core of the first plurality of cores remains enabled, and lowering at least one of an operating frequency and a supply voltage of the one core of the second plurality of cores as demand drops below a next lower threshold.

12. The non-transitory machine readable medium of claim 11 wherein said method further comprises lowering at least one of a supply voltage and an operating frequency of said one core in response to lower demand being offered to said multi-core processor.

13. The non-transitory machine readable medium of claim 12 wherein said method further comprises raising at least one of a supply voltage and an operating frequency of said one core in response to higher demand being offered to said multi-core processor.

14. The non-transitory machine readable medium of claim 11 wherein said method further comprises raising at least one of a supply voltage and an operating frequency of said one core in response to higher demand being offered to said multi-core processor.

15. The multi-core processor of claim 1 wherein the power management hardware is to lower at least one of a supply voltage and an operating frequency of each additional core to a lower operating level before disablement.

16. The multi-core processor of claim 1 wherein the power management hardware is to enable an additional core of the second plurality of cores for each continued increase in demand above a next higher threshold without enabling any of the first plurality of cores until the second plurality of cores is enabled, and enable an additional core of the first plurality of cores for each continued increase in demand above a next higher threshold until the first plurality of cores is also enabled.

17. The multi-core processor of claim 1 wherein the power management hardware is to lower at least one of a supply voltage and an operating frequency of said one core in response to lower demand.

18. The multi-core processor of claim 1 wherein the power management hardware is to raise at least one of a supply voltage and an operating frequency of said one core in response to higher demand.

19. The method of claim 6 further comprising lowering at least one of a supply voltage and an operating frequency of each additional core to a lower operating level before disablement.

20. The non-transitory machine readable medium of claim 11 wherein said method further comprises lowering at least one of a supply voltage and an operating frequency of each additional core to a lower operating level before disablement.

Assignees

• George Varghese
• Jahagirdar Sanjeev S
• Marr Deborah T
• Intel Corp

Inventors

• George Varghese
• Jahagirdar Sanjeev S
• Marr Deborah T

Classifications

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• Y02B60/121

  Cross-Sectional Technologies · mapped topic

• Y02B60/142

  Cross-Sectional Technologies · mapped topic