Dynamic bit-width modification of internal pointers of a virtual machine

Patent metadata

Field	Value
Publication number	US-9569234-B2
Application number	US-201414524219-A
Country	US
Kind code	B2
Filing date	Oct 27, 2014
Priority date	Oct 27, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A content processing device and corresponding method for processing source code are disclosed. The method may include receiving source code with a virtual machine operating on a hardware platform with an inherent address-pointer-bit-width and generating, from the source code, executable code that includes internal address pointers to objects in the virtual machine heap. One or more runtime conditions may be monitored and a size of a bit-width for the internal address pointers in the virtual machine may be adjusted, with or without associated changes to create optimized layout of the objects in the virtual machine heap, based upon one or more runtime conditions.

First claim

What is claimed is:

1. A method for processing source code comprising:
receiving source code with a virtual machine operating on a hardware platform that has a maximum inherent address-pointer-bit-width;
generating non-optimized executable code from the source code;
creating, using meta-data information of different fields and bit-width sizes for internal pointer fields in map objects, an optimized object layout for different objects in a virtual machine heap;
generating optimized code that utilizes the optimized object layout as described by the map objects to access object properties in less time or with fewer instructions than the non-optimized executable code, the optimized code including run-time checks to confirm that an object has a known layout as described by the map objects, the optimized code including internal address pointers to objects in the virtual machine heap;
executing the optimized code on the hardware platform utilizing the optimized object layout;
monitoring one or more runtime conditions in connection with execution of the optimized code; and
adjusting a size of a bit-width for the internal address pointers based upon the one or more runtime conditions.

2. The method of claim 1 , wherein generating optimized code includes:
generating non-optimized executable code with internal address pointers that have a default bit-width;
wherein adjusting the size of the bit-width of the internal address pointers includes generating optimized code with internal address pointers that have an adjusted size that is larger or smaller than the default bit-width, but smaller than the maximum inherent address-pointer-bit-width.

3. The method of claim 1 , wherein generating optimized code includes: generating non-optimized executable code with internal address pointers that have a default bit-width;
wherein the default bit-width is the maximum inherent address-pointer-bit-width and the adjusted size is a bit size that is less than or equal to the maximum inherent address-pointer-bit-width.

4. The method of claim 3 , wherein the maximum inherent address-pointer-bit-width is 64 bits and the adjusted size is one of 16 bits, 32 bits, 48 bits, or 64 bits.

5. The method of claim 4 , wherein monitoring includes monitoring an availability of memory on the hardware platform.

6. The method of claim 1 , wherein monitoring includes: monitoring an address range of the optimized code.

7. The method of claim 1 , including: dedicating general purpose registers on the hardware platform to store the internal address pointers; and
updating the stored address pointers by bitwise-inserting each address pointer in lower bits of a corresponding general purpose register used as an address register.

8. A non-transitory, tangible computer readable storage medium, encoded with processor readable instructions to perform a method for processing source code, the method comprising:
receiving source code with a virtual machine operating on a hardware platform that has a maximum inherent address-pointer-bit-width;
generating non-optimized executable code from the source code;
creating, using meta-data information of different fields and bit-width sizes for internal pointer fields in map objects, an optimized object layout for different objects in a virtual machine heap;
generating optimized code that utilizes the optimized object layout as described by the map objects to access object properties in less time or with fewer instructions than the non-optimized executable code, the optimized code including run-time checks to confirm that an object has a known layout as described by the map objects, the optimized code including internal address pointers to objects in the virtual machine heap;
executing the optimized code on the hardware platform;
monitoring one or more runtime conditions in connection with execution of the optimized code; and
adjusting a size of a bit-width for the internal address pointers based upon the one or more runtime conditions.

9. The non-transitory, tangible computer readable storage medium of claim 8 , wherein generating optimized code includes:
generating non-optimized executable code with internal address pointers that have a default bit-width;
wherein adjusting the size of the bit-width of the internal address pointers includes generating optimized code with internal address pointers that have an adjusted size that is larger or smaller than the default bit-width, but smaller than the maximum inherent address-pointer-bit-width.

10. The non-transitory, tangible computer readable storage medium of claim 8 , wherein generating optimized code includes:
generating non-optimized executable code with internal address pointers that have a default bit-width;
wherein the default bit-width is the maximum inherent address-pointer-bit-width and the adjusted size is a bit size that is less than or equal to the maximum inherent address-pointer-bit-width.

11. The non-transitory, tangible computer readable storage medium of claim 10 , wherein the maximum inherent address-pointer-bit-width is 64 bits and the adjusted size is one of 16 bits, 32 bits, 48 bits, or 64 bits.

12. The non-transitory, tangible computer readable storage medium of claim 11 , wherein monitoring includes monitoring an availability of memory on the hardware platform.

13. The non-transitory, tangible computer readable storage medium of claim 8 , wherein monitoring includes: monitoring an address range of the optimized code.

14. The non-transitory, tangible computer readable storage medium of claim 8 , wherein the method includes:
dedicating general purpose registers on the hardware platform to store the internal address pointers; and
updating the stored address pointers by bitwise-inserting each address pointer in lower bits of a corresponding general purpose register.

15. A computing device comprising:
a network interface that receives source code from a remote location;
a hardware platform that is coupled to the network interface, the hardware platform including a maximum inherent address-pointer-bit-width;
a virtual machine that generates non-optimized executable code and optimized code from the source code, the optimized code including internal address pointers to objects in a virtual machine heap, the virtual machine including:
an object layout optimizer that generates, using meta-data information of different fields and bit-width sizes for internal pointer fields in map objects, an optimized object layout for different objects in the virtual machine heap, the optimized code including run-time checks to confirm that an object has a known layout as described by the map objects;
an optimizing compiler that utilizes the optimized object layout as described by the map objects to access object properties in less time or with fewer instructions than the non-optimized executable code;
an execution component that executes the optimized code on the hardware platform utilizing the optimized object layout;
a runtime condition monitor that monitors one or more runtime conditions in connection with execution of the optimized code; and
a pointer-size selection component that adjusts a size of a bit-width for the internal address pointers based upon the one or more runtime conditions.

16. The computing device of claim 15 , wherein the virtual machine includes:
a non-optimizing compiler that generates non-optimized executable code with internal address pointers that have a default bit-width;
wherein the optimizing compiler generates optimized code with internal address pointers that have an adjusted size that is less t

Assignees

• Qualcomm Innovation Ct Inc

Inventors

• De Subrato K
• Conrod Derek J
• Sule Dineel D

Classifications

• G06F8/443 Primary

  Optimisation · CPC title

• G06F9/45516

  Runtime code conversion or optimisation · CPC title

• G06F9/4552 Primary

  Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM · CPC title