Method and apparatus for a zero voltage processor
US-9223390-B2 · Dec 29, 2015 · US
US9568983B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9568983-B1 |
| Application number | US-201314106402-A |
| Country | US |
| Kind code | B1 |
| Filing date | Dec 13, 2013 |
| Priority date | Apr 29, 2010 |
| Publication date | Feb 14, 2017 |
| Grant date | Feb 14, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
External jolts, such as those occurring during shipment, may inadvertently activate an electronic device. Such inadvertent activations may result in the electronic device entering an active mode during shipment, draining battery power. This document describes a power cut off mode that prevents inadvertent device activations and minimizes current consumption during shipment or storage of a device. This conserves battery power for operational use by the user.
Opening claim text (preview).
What is claimed is: 1. A method comprising: pausing operation of an electronic device; terminating one or more processes running on the electronic device; sending a signal to stop operation of one or more components of the electronic; designating a source for a wakeup signal; configuring a power management integrated circuit of the electronic device for a power cut off mode, wherein the configuring the power management integrated circuit includes configuring a reset signal pin on the power management integrated circuit as an input/output interface, and wherein, in the power cut off mode, wait-for-interrupt circuitry in the power management integrated circuit is operational; and setting a real-time clock to remain active with the power management integrated circuit in the power cut off mode. 2. The method as recited in claim 1 , further comprising, prior to the activating, configuring the electronic device for the power cut off mode by setting at least one power regulator to transition to an off state to power down a central processor unit of the electronic device when the power cut of mode is activated. 3. The method as recited in claim 2 , wherein setting the at least one power regulator comprises setting at least one of a switching regulator or a linear regulator in a power management integrated circuit to transition to the off state, the configuring the electronic device for the power cut off mode further comprising: clearing a restart register bit in the power management integrated circuit to prevent a restart; and turning off a universal serial bus input voltage, wherein the reset signal pin is configured to place the power management integrated circuit into the power cut off mode when set to a low voltage. 4. The method as recited in claim 1 , further comprising: receiving a wakeup signal while the electronic device is in the power cut off mode; and at least partially in response to the wakeup signal being received for a duration less than a threshold duration, maintaining the power cut off mode. 5. The method as recited in claim 1 , further comprising: receiving a wakeup signal while the electronic device is in the power cut off mode; and at least partially in response to the wakeup signal being received for a duration that exceeds a threshold duration, causing powering up of at least a portion of the electronic device. 6. The method as recited in claim 5 , wherein causing powering up of at least the portion of the electronic device comprises causing activation of at least one power regulator to power up a central processor unit of the electronic device. 7. The method as recited in claim 1 , further comprising activating the power cut off mode in response, at least in part, to at least one of: determining that a threshold amount of time has elapsed since a user action; determining that a current battery status is below a threshold value; or determining that the electronic device has not completed an initial setup. 8. An electronic device comprising: a central processor unit; a non-transitory computer-readable medium coupled to the central processor unit; a real-time clock; and a power cut off module, maintained in the computer-readable medium and configured to be executed by the central processor unit to: designate a source for a wakeup signal; set the real-time clock to remain active; retain operation of a wait-for-interrupt circuitry; and activate a power cut off mode for the electronic device, wherein the power cut off mode comprises powering down the central processor unit and, in the power cut off mode, power consumption of the electronic device is no more than about 0.034 mA. 9. The electronic device as recited in claim 8 , wherein the power cut off module is further configured to be executed by the central processor unit to: pause operation of the electronic device; terminate one or more processes running on the electronic device; and send a signal to stop operation of one or more components in the electronic device. 10. The electronic device as recited in claim 8 , further comprising a power switch as the source for the wakeup signal. 11. The electronic device as recited in claim 8 , wherein the power cut off module is further configured to be executed by the central processor unit to: set at least one of a switching regulator or a linear regulator in a power management integrated circuit to transition to an off state in response to activation of the power cut off mode; clear a restart register bit in the power management integrated circuit; turn off a universal serial bus input voltage; and configure a reset signal pin on the power management integrated circuit as a input/output interface, the reset signal pin configured to place the power management integrated circuit into the power cut off mode when set to a low voltage. 12. The electronic device as recited in claim 8 , wherein the power cut off module is further configured to be executed by the central processor unit to activate the power cut off mode at least partly in response to determining that a condition has been met, the power cut off mode configuring the electronic device to await a sustained wakeup signal before powering up the electronic device from the power cut off mode. 13. The electronic device as recited in claim 12 , wherein the power cut off module is further configured to be executed by the central processor unit to determine that the condition has been met based at least in part on at least one of: determining that a threshold amount of time has elapsed since a user action; determining that a current battery status is below a threshold value; or determining that the electronic device has not completed an initial setup. 14. The electronic device as recited in claim 12 , wherein the sustained wakeup signal comprises a wakeup signal having a duration of at least 25 milliseconds. 15. A method comprising: receiving, at an electronic device, a wakeup signal while the electronic device is in a power cut off mode, wherein, in the power cut off mode, a circuit of the electronic device is configured to receive a wakeup signal; a central processor unit, switching regulators, and linear regulators of the electronic device are powered down; and a power management integrated circuit of the electronic device retains the operation of a real time clock and wait-for-interrupt circuitry; and based at least in part on a duration of the wakeup signal exceeding a threshold duration, the circuit causing at least a portion of the electronic device to power up from the power cut off mode. 16. The method as recited in claim 15 , further comprising, prior to receiving the wakeup signal: pausing operation of an electronic device; terminating one or more processes running on the electronic device; sending a signal to stop operation of one or more components of the electronic device; designating a source for a wakeup signal; setting a real-time clock to remain active; and activating the power cut off mode for the electronic device to power down the central processor unit. 17. The method as recited in claim 15 , further comprising, prior to the activating, configuring the electronic device for the power cut off mode by: setting at least one power regulator to transition to an off state to power down the central processor unit of the electronic device; and configuring the circuit to maintain the power cut off mode until receipt of the wakeup signal exceeding the threshold duration. 18. The method as recited in claim 15 , wherein ca
by software initiated power-off · CPC title
Monitoring of events, devices or parameters that trigger a change in power modality · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.