Active cable testing

US9568530B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9568530-B2
Application numberUS-201414527560-A
CountryUS
Kind codeB2
Filing dateOct 29, 2014
Priority dateOct 29, 2014
Publication dateFeb 14, 2017
Grant dateFeb 14, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments of the present disclosure provide configurations for testing arrangements for testing multi-lane active cables. In one embodiment, a testing arrangement may comprise a testing module comprising a pattern generator to be coupled with an active cable having a plurality of lanes to generate a test pattern to be transmitted over the active cable, wherein the test pattern is to be transmitted at least over two or more lanes of the active cable that are concatenated, and a processing unit to be coupled with the active cable to process a result of the transmission of the test pattern over the active cable. The arrangement may further include a plurality of testing cables to concatenate two or more of the lanes of the active cable, to enable the transmission of the test pattern over the concatenated lanes of the active cable. Other embodiments may be described and/or claimed.

First claim

Opening claim text (preview).

What is claimed is: 1. A cable testing arrangement, comprising: a testing module comprising a pattern generator to be coupled with an active cable having a plurality of lanes to generate a test pattern to be transmitted over the active cable, wherein the test pattern is to be transmitted at least over two or more lanes of the active cable that are concatenated in loopback connections, and a processing unit to be coupled with the active cable to process a result of the transmission of the test pattern over the active cable, wherein to process includes to determine a bit error rate (BER) associated with the transmission of the test pattern over the active cable; and a plurality of testing cables to concatenate the two or more of the plurality of lanes of the active cable in the loopback connections, to enable the transmission of the test pattern over the two or more lanes of the active cable concatenated in the loopback connections. 2. The cable testing arrangement of claim 1 , wherein the plurality of testing cables is to concatenate all of the lanes of the active cable, wherein the pattern generator is to inject the test pattern into the concatenated lanes of the active cable, wherein the processing unit is to process a result of the injection of the test pattern into the concatenated lanes after the test pattern traversed the concatenated lanes of the active cable. 3. The cable testing arrangement of claim 1 , wherein the plurality of testing cables is to concatenate all of the lanes of the active cable, except one lane, wherein the pattern generator is to inject the test pattern into the concatenated lanes of the active cable and the one lane that is not concatenated with other lanes. 4. The cable testing arrangement of claim 3 , wherein the pattern generator is to: connect with a first end of the one lane to enable the test pattern injection into the one lane; and connect with the concatenated lanes via one of the testing cables to enable the test pattern injection into the concatenated lanes. 5. The cable testing arrangement of claim 4 , wherein the processing unit is to connect with a second end of the one lane, to process a result of the injection of the test pattern into the one lane. 6. A method, comprising: concatenating in loopback connections two or more of a plurality of lanes of an active cable with a plurality of testing cables; connecting a pattern generator of a testing module with the two or more lanes that are concatenated in the loopback connections, to enable transmission of a test pattern generated by the pattern generator over the two or more lanes concatenated in the loopback connections; and communicatively coupling a processing unit of the testing module with the active cable, to process a result of the transmission of the test pattern over the active cable, wherein to process includes to determine a bit error rate (BER) associated with the transmission of the test pattern over the active cable. 7. The method of claim 6 , wherein two or more of a plurality of lanes include all of the plurality of lanes, wherein communicatively coupling a processing unit with the active cable includes connecting the processing unit to the concatenated lanes. 8. The method of claim 6 , wherein two or more of a plurality of lanes of the active cable include all of the plurality of lanes except one lane, wherein connecting a pattern generator includes connecting the pattern generator to the concatenated lanes and to the one lane; and communicatively coupling a processing unit includes connecting the processing unit to the one lane. 9. The method of claim 8 , further comprising: connecting the pattern generator with a first end of the one lane; and connecting the processing unit with a second end of the one lane. 10. The method of claim 9 , wherein connecting the pattern generator with a first end of the one lane includes connecting the pattern generator with the first end via a first breakout board coupled with a first end of the active cable. 11. The method of claim 10 , wherein connecting the processing unit with a second end of the one lane includes connecting the processing unit with the second end via a second breakout board coupled with a second end the active cable, wherein the first end and second end provide selective connections for the plurality of testing cables with the two or more of the plurality of lanes of the active cable, wherein the first end of the one lane corresponds to the first end of the active cable and wherein the second end of the one lane corresponds to the second end of the active cable. 12. The method of claim 6 , wherein concatenating two or more of a plurality of lanes of an active cable with a plurality of testing cables includes concatenating the two or more lanes with selected ones of: a coaxial cable, a twin-axial cable, or a twisted pair cable. 13. The method of claim 6 , wherein concatenating two or more of a plurality of lanes of an active cable with a plurality of testing cables includes concatenating the two or more lanes with the testing cables that have a first length that is equal to or greater than a second length of each of the lanes of the active cable. 14. The method of claim 6 , wherein the active cable comprises one of an active optical cable or an active electric cable. 15. A method, comprising: transmitting a test pattern over an active cable having a plurality of lanes, including transmitting the test pattern over two or more lanes that are concatenated in loopback connections; and processing a result of transmitting the test pattern over the active cable, including determining an error characteristic associated with transmitting the test pattern over the active cable, wherein determining the error characteristic includes determining a bit error rate (BER) associated with transmitting the test pattern over all of the plurality of lanes of the active cable. 16. The method of claim 15 , wherein transmitting a test pattern includes injecting the test pattern into the two or more lanes concatenated with a plurality of testing cables, wherein each of the plurality of testing cables comprises a first length that is equal to or greater than a second length of each of the lanes of the active cable. 17. The method of claim 16 , wherein the two or more lanes comprise all of the plurality of lanes of the active cable. 18. The method of claim 17 , wherein processing a result of transmitting the test pattern over the active cable includes: based on a result of the determined error characteristic, determining whether to test each of the plurality of lanes of the active cable separately. 19. The method of claim 16 , wherein the two or more lanes comprise all of the plurality of lanes of the active cable except one lane, wherein transmitting a test pattern over an active cable further comprises injecting the test pattern into the one lane that is not concatenated with other lanes. 20. The method of claim 19 , wherein processing a result of transmitting the test pattern includes: determining a result of injecting the test pattern into the one lane that is not concatenated with other lanes; and determining the error characteristic based on the determined result. 21. The method of claim 15 , wherein transmitting a test pattern over an active cable includes transmitting over the active cable one of: a pseudo-random binary sequence (PRBS), a quasi-random signal source (QRSS), bridgetap, or multipat.

Assignees

Inventors

Classifications

  • H04B3/46Primary

    Monitoring; Testing · CPC title

  • G01R31/58Primary

    Testing of lines, cables or conductors (testing of electric windings G01R31/72) · CPC title

  • with a light emitter being disposed at one fibre or waveguide end-face, and a light receiver at the other end-face · CPC title

  • Repeater circuits (H04B3/58 takes precedence) · CPC title

  • G01R31/021Primary

    Physics · mapped topic

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What does patent US9568530B2 cover?
Embodiments of the present disclosure provide configurations for testing arrangements for testing multi-lane active cables. In one embodiment, a testing arrangement may comprise a testing module comprising a pattern generator to be coupled with an active cable having a plurality of lanes to generate a test pattern to be transmitted over the active cable, wherein the test pattern is to be transm…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H04B3/46. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).