Electronic component

Patent metadata

Field	Value
Publication number	US-9565755-B2
Application number	US-201615062477-A
Country	US
Kind code	B2
Filing date	Mar 7, 2016
Priority date	Mar 19, 2009
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.

First claim

What is claimed is:

1. An electronic component comprising:
a wiring board including a first electrode pad on a surface thereof; and
a plurality of circuit boards having slits that are fitted to each other, the circuit boards being disposed to stand on the wiring board, and including an interconnection for connecting the first electrode pad to a second electrode pad of a semiconductor element to be mounted on the wiring board, the interconnection and the first electrode pad is connected with any one of a solder and a conductive adhesive, wherein
the circuit board comprises:
a first resin film having the interconnection formed on one main surface thereof; and
a second resin film formed on the interconnection and the first resin film,

at least one of the first resin film and the second resin film has an opening formed on an end portion of the interconnection to expose the interconnection therefrom, and
the end portion of the interconnection is connected to any one of the first electrode pad and the second electrode pad.

2. The electronic component according to claim 1 , wherein
the plurality of the circuit boards are assembled in a lattice pattern.

3. The electronic component according to claim 1 , wherein the plurality of the circuit boards are radially assembled.

Assignees

• Fujitsu Ltd

Inventors

• Nakanishi Teru
• Hayashi Nobuyuki
• Morita Masaru
• Yoneda Yasuhiro

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/255

  of outermost layers of multilayered bumps, e.g. material of a coating · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title