Sampling period control circuit capable of controlling sampling period

Patent metadata

Field	Value
Publication number	US-9565374-B2
Application number	US-201514632418-A
Country	US
Kind code	B2
Filing date	Feb 26, 2015
Priority date	Mar 14, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A sampling period control circuit according to an example embodiment of the inventive concepts is configured to derive a ramp voltage range of a row signal when analyzing a previous row signal in order to control a ramp voltage range of a next row signal.

First claim

What is claimed is:

1. A sampling period control circuit configured to derive a ramp voltage range of a row signal when analyzing a previous row signal in order to control a ramp voltage range of a next row signal, the sampling period control circuit comprising:
a row range detector configured to detect a substantial maximum value and minimum value of a row scanning range by analyzing the previous row signal;
a row range controller configured to reset a scan ramp maximum value and a scan ramp minimum value based on an error range in the detected substantial maximum value and minimum value of the row scanning range;
a ramp controller configured to control scanning and comparing a ramp voltage of a corresponding row using the scan ramp maximum value and the scan ramp minimum value; and
a correlated double sampling (CDS) circuit configured to perform a CDS operation on a result of the comparison received from the ramp controller,
wherein the row range detector is configured to detect the substantial maximum value and minimum value of the row scanning range from data fed back from the CDS circuit, the data relating to the previous row signal.

2. The sampling period control circuit of claim 1 , wherein the row range controller is configured to select a higher value between a minimum value of a preset ramp scanning range and a minimum value of a scanning range measured in the previous row signal as the scan ramp minimum value.

3. The sampling period control circuit of claim 1 , wherein the row range controller is configured to select a lower value between a maximum value of the preset ramp scanning range and a maximum value of a scanning range measured in the previous row signal as the scan ramp maximum value.

4. The sampling period control circuit of claim 2 , wherein the row range controller is configured to deduct the error range to obtain the scan ramp minimum value.

5. The sampling period control circuit of claim 3 , wherein the row range controller is configured to add the error range to obtain the scan ramp maximum value.

6. The sampling period control circuit of claim 1 , further comprising:
a level compensator configured to adjust a count value read from each column in response to an output of the row range controller and the CDS circuit based on an original count value.

7. A sampling period control circuit configured to control a ramp voltage scanning range and a sampling period of a previous row signal to be different from a ramp voltage scanning range and a sampling period of a next row signal, the sampling period control circuit comprising:
a row range detector configured to detect a substantial maximum value and minimum value of a row scanning range by analyzing the previous row signal;
a row range controller configured to reset a scan ramp maximum value and a scan ramp minimum value based on an error range in the substantial maximum value and minimum value of the row scanning range;
a ramp controller configured to control scanning and comparing a ramp voltage of a corresponding row by using the scan ramp maximum value and the scan ramp minimum value; and
a correlated double sampling (CDS) circuit configured to perform a CDS operation on a result of comparison received from the ramp controller,
wherein the row range detector is configured to detect the substantial maximum value and minimum value of the row scanning range from data fed back from the CDS circuit, the data relating to the previous row signal.

8. The sampling period control circuit of claim 7 , wherein the row range controller is configured to select a higher value between a minimum value of a preset ramp scanning range and a minimum value of a scanning range measured in the previous row signal as the scan ramp minimum value.

9. The sampling period control circuit of claim 7 , wherein the row range controller is configured to select a lower value between a maximum value of the preset ramp scanning range and a maximum value of a scanning range measured in the previous row signal as the scan ramp maximum value.

10. The sampling period control circuit of claim 7 , wherein the ramp voltage scanning range of the next row signal is reduced compared to the ramp voltage scanning range of the previous row signal.

11. The sampling period control circuit of claim 10 , wherein the sampling period of the next row signal is shorter than the sampling period of the previous row signal.

12. A device, comprising:
a sampling period control circuit configured to,
measure a voltage range of a first scan signal, and
adjust a voltage range of a second scan signal based on the measured voltage range and an error range associated with the measured voltage range of the first scan signal, the second scan signal being subsequent to the first scan signal.

13. The device of claim 12 , wherein the sampling period control circuit is configured to perform a sampling operation using the second scan signal having the adjusted voltage range.

14. The sampling period control circuit of claim 12 , wherein the sampling period control circuit is configured to select a higher value between a minimum value of a preset voltage range and a minimum value of the measured voltage range as a minimum value of the adjusted voltage range.

15. The sampling period control circuit of claim 12 , wherein the sampling period control circuit is configured to select a lower value between a maximum value of a preset voltage range and a maximum value of the measured voltage range as a maximum value of the adjusted voltage range.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Tae-Chan
• Han Gab-Soo
• Min Dong-Ki
• Jung Jung-Hoon

Classifications

• H04N25/616 Primary

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H04N25/772

  comprising A/D, V/T, V/F, I/T or I/F converters · CPC title

• H04N25/573 Primary

  the logarithmic type · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/53

  Control of the integration time · CPC title