Power switch ramp rate control using selectable daisy-chained connection of enable to power switches or daisy-chained flops providing enables

Patent metadata

Field	Value
Publication number	US-9564898-B2
Application number	US-201514622111-A
Country	US
Kind code	B2
Filing date	Feb 13, 2015
Priority date	Feb 13, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

In an embodiment, an integrated circuit may include one or more power gated blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power gated block and a block enable clock. The power gated block may generate local block enables to various power switch segments in the power gated block. In particular, the power gated block may include a set of series-connected flops that receive the block enable from the power manager circuit. The power gated block may include a set of multiplexors (muxes) that provide the local block enables for each power switch segment. One input of the muxes is coupled to the block enable, and the other input is coupled to another enable propagated through one of the other power switch segments. Accordingly, the muxes may be controlled to select the propagated enables or the input block enable.

First claim

What is claimed is:

1. A power control apparatus comprising:
a plurality of power switch segments each comprising a plurality of power switches, wherein:
the power switches are coupled to a first power rail that is powered to a power supply voltage during use;
the power switches are coupled to one or more power supply inputs of a block of circuits; and
the power switches in a given power switch segment logically share a power switch enable input to the given power switch segment;

a plurality of flops coupled in series, wherein a first flop in the series is coupled to a global power switch enable input;
a plurality of multiplexors, wherein:
each multiplexor includes a first input coupled to an output of a given flop of the plurality of flops and a second input coupled to a power switch enable output of one of the plurality of power switch segments; and
each multiplexor has an output coupled to the power switch enable input of a respective power switch segment of the plurality of power switch segments; and

clock circuitry configured to:
generate a clock for the plurality of flops; and
during a power up cycle of the block and during a time period that the one or more power supply inputs are charging to a voltage supplied from the first power rail, sequence a clock frequency at which the clock toggles through a preselected plurality of frequencies, each frequency of the plurality of frequencies used for a preselected number of clock pulses at that frequency.

2. The power control apparatus as recited in claim 1 wherein at least two multiplexors of the plurality of multiplexors have the first input coupled to the output of the given flop.

3. The power control apparatus as recited in claim 1 wherein the multiplexors include a select input that selects either the first input or the second input as the output, and the power control apparatus further comprises circuitry configured to generate the select input.

4. The power control apparatus as recited in claim 3 wherein the circuitry is configured to select the second input in response to reset of the apparatus.

5. The power control apparatus as recited in claim 4 wherein the circuitry is programmable to select the first input subsequent to reset.

6. The power control apparatus as recited in claim 1 wherein the clock frequency is initially at a first frequency of the plurality of frequencies and increases to one or more additional frequencies of the plurality of frequencies during the power up cycle.

7. The power control apparatus as recited in claim 1 wherein the plurality of flops are powered from the first power rail directly.

8. An integrated circuit comprising:
a plurality of power switches coupled to a supply voltage node and configured to provide supply voltage to a circuit block responsive to a plurality of enables, wherein each of the plurality of power switches is coupled to one of the plurality of enables;
a power control circuit configured to generate the plurality of enables for the plurality of power switches responsive to an input block enable, wherein the power control circuit comprises:
a plurality of series-connected clocked storage devices, wherein a first clocked storage device is coupled to receive the input block enable; and
a plurality of multiplexors, each of the plurality of multiplexors coupled to an output of one of the plurality of series-connected clocked storage devices and coupled to a block enable propagated through a respective subset of the plurality of power switches, wherein an output of each of the plurality of multiplexors is one of the plurality of enables; and

clock circuitry configured to generate a clock for the plurality of flops, and, during a power up cycle of the block and during a time period that the one or more power supply inputs are charging to a voltage supplied from the first power rail, the clock circuitry is configured to modify a clock frequency at which the clock toggles through a series of predetermined frequencies in a predetermined pattern.

9. The integrated circuit as recited in claim 8 wherein each of the plurality of multiplexors includes a multiplexor select input, and wherein the multiplexor select input defaults to selecting the block enable propagated through the respective subset, whereby the plurality of power switches are logically daisy-chained to receive the enable.

10. The integrated circuit as recited in claim 9 wherein each of the plurality of block enables are passed through a plurality of series-connected buffers to enable the respective subset, wherein the block enable propagated through the respective subset is an output of the plurality of series-connected buffers.

11. The integrated circuit as recited in claim 8 wherein the frequency is initially at a first frequency and increases to one or more additional frequencies during the power up cycle.

12. The integrated circuit as recited in claim 11 wherein the clock circuitry is configured to divide an input clock by a first programmable divisor to generate the clock at the first frequency, then divide the input by a second programmable divisor to generate a second frequency that is one of the one or more additional frequencies.

13. The integrated circuit as recited in claim 8 wherein the plurality of flops are powered from the supply voltage node directly.

14. The integrated circuit as recited in claim 8 wherein the plurality of flops are located outside of the circuit block, in a second circuit block that is powered by the supply voltage node.

15. The integrated circuit as recited in claim 14 wherein the second circuit block remains powered when the circuit block is powered down.

16. A method comprising:
determining that a power gated block in an integrated circuit is to be powered up;
asserting a block enable and enabling an enable clock to the power gated block responsive to the determining;
propagating the block enable through a plurality of series-connected clocked storage devices, generating a plurality of propagated block enables;
activating a plurality of power switch segments in the power gated block, wherein each of the plurality of power switch segments are coupled to receive an enable from one of a plurality of multiplexors, and each of the plurality of multiplexors selects between one of the plurality of propagated block enables and a second enable that is output from another one of the plurality of power switch segments, and the second enable is a delayed version of the enable received by the other one of the plurality of power switch segments; and
varying a frequency of a clock to the plurality of series-connected clocked storage devices during the propagating and during a time period that one or more power supply inputs to the power gated block are charging to a voltage supplied from the first power rail, wherein the varying is performed in a plurality of phases, each phase have a preselected frequency at which the clock operates for a predetermined duration.

17. The method as recited in claim 16 wherein the varying comprising monotonically increasing the frequency.

18. The power control apparatus as recited in claim 1 wherein the clock circuitry is configured to sequence the clock frequency in a monotonically increasing pattern.

19. The integrated circuit as recited in claim 8 wherein the clock circuitry is configured to modify the clock frequency in a monotonically increasing pattern.

Assignees

• Apple Inc

Inventors

• Suzuki Shingo
• Krishnamurthy Harsha
• Catovic Edvin
• Goel Rajat
• Gopalan Manoj

Classifications

• H03K19/0013

  in field effect transistor circuits · CPC title

• H03K19/00361 Primary

  in field effect transistor circuits · CPC title

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title