Circuitry and method for measuring negative bias temperature instability (NBTI) and hot carrier injection (HCI) aging effects using edge sensitive sampling

Patent metadata

Field	Value
Publication number	US-9564884-B1
Application number	US-201514791444-A
Country	US
Kind code	B1
Filing date	Jul 4, 2015
Priority date	Apr 13, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Toggling functional critical path timing sensors measure delays in toggling functional critical paths that continuously receive patterns from an aging pattern generator. Wear is accelerated. A margin delay adjustment controller sweeps margin delays until failures occur to measure delays. The margin delay is then adjusted in functional critical path timing sensors that add the margin delay to functional critical paths that carry user data or chip controls during normal operation. When the path delays fail to meet requirements, the functional critical path timing sensors signal a controller to increase VDD. When no failures occur over a period of time, the controller decreases VDD. Wear on the toggling functional critical paths is accelerated using both toggle and low-transition-density patterns. Circuit aging is compensated for by increasing margin delays to timing sensors.

First claim

We claim:

1. A wear-sensing integrated circuit comprising:
an aging pattern generator that generates a plurality of patterns to accelerate wear of transistors;
a plurality of toggling functional critical paths that receive patterns generated by the aging pattern generator;
a plurality of toggling functional critical path timing sensors, each receiving an output of a toggling functional critical path in the plurality of toggling functional critical paths;
a plurality of fail signals generated by the plurality of toggling functional critical path timing sensors, wherein a fail signal is generated when a delay through a toggling functional critical path exceeds a timing requirement; and
a margin delay adjustment controller that receives the fail signals generated by the plurality of toggling functional critical path timing sensors, the margin delay adjustment controller adjusting a margin value in response to receiving the fail signals;
wherein the margin value increases over time as the wear-sensing integrated circuit ages during a lifetime of the wear-sensing integrated circuit.

2. The wear-sensing integrated circuit of claim 1 wherein the timing requirement is a set-up time to a clocked register plus a margin delay of a margin delay buffer;
wherein the fail signals are generated when delays through the toggling functional critical path plus the margin delay fails to meet the set-up time to the clocked register.

3. The wear-sensing integrated circuit of claim 2 wherein the toggling functional critical path timing sensor comprises:
a margin delay buffer that receives an output of a toggling functional critical path;
a first register that receives an output of the margin delay buffer;
a second register that receives an input of the toggling functional critical path; and
a compare gate that compares an output of the first register to an output of the second register to generate the fail signal when the output of the first register does not match the output of the second register.

4. The wear-sensing integrated circuit of claim 3 wherein a margin delay through the margin delay buffer is variable;
wherein the margin delay adjustment controller sweeps the margin delay across a range of values to test for timing failures to determine the margin value.

5. The wear-sensing integrated circuit of claim 4 wherein the aging pattern generator generates the plurality of patterns to accelerate wear of transistors in the plurality of toggling functional critical paths, wherein the patterns comprise:
a toggling pattern that toggles a first input to a first toggling functional critical path in the plurality of toggling functional critical paths, wherein the first toggling functional critical path has accelerated wear due to Hot Carrier Injection (HCI) effects.

6. The wear-sensing integrated circuit of claim 5 wherein the aging pattern generator generates the plurality of patterns to accelerate wear of transistors in the plurality of toggling functional critical paths, wherein the patterns further comprise:
a low-level low-density pattern that is applied to a second input to a second toggling functional critical path in the plurality of toggling functional critical paths, wherein the second toggling functional critical path has accelerated wear due to Negative Bias Temperature Instability (NBTI) effects;
wherein the aging pattern generator generates the low-level low-density pattern with a duty cycle of less than 10%, wherein no more than one high pulse is generated for every X clock periods, wherein X is at least 10, wherein the second input remains in a low state for X−1 clock periods; and
a high-level low-density pattern that is applied to a third input to a third toggling functional critical path in the plurality of toggling functional critical paths, wherein the third toggling functional critical path has accelerated wear due to Negative Bias Temperature Instability (NBTI) effects;
wherein the aging pattern generator generates the high-level low-density pattern with a duty cycle of more than 90%, wherein no more than one low pulse is generated for every X clock periods, wherein X is at least 10, wherein the third input remains in a high state for X−1 clock periods.

7. The wear-sensing integrated circuit of claim 5 wherein the toggling functional critical paths comprise copies of functional critical paths that carry user data or control information during a normal operating mode of the wear-sensing integrated circuit.

8. The wear-sensing integrated circuit of claim 5 wherein the toggling functional critical paths comprise representational critical paths having a string of gates with a number of gates exceeding a maximum number of gates in any functional critical path in the wear-sensing integrated circuit, or a gate with a fan-out exceeding a maximum fan-out of any functional critical path in the wear-sensing integrated circuit.

9. The wear-sensing integrated circuit of claim 5 further comprising:
a plurality of registers for storing internal signals in response to a clock;
combinatorial logic between inputs and outputs of the plurality of registers;
a plurality of functional critical paths being among a top 10% of paths in the combinatorial logic sorted by delay;
wherein the plurality of functional critical paths carry real data and control information during normal modes of operation rather than being dummy paths having no functional use; and
a functional critical path timing sensor for each functional critical path in the plurality of functional critical paths, each functional critical path driving a next-level input to a next-level register in the plurality of registers, wherein the functional critical path timing sensor generates a functional timing failure signal when data passing through a functional critical path arrives at the next-level input after a trigger time;
wherein the trigger time is a margin time plus a set-up time for the next-level input relative to the clock to the next-level register;
wherein the margin value from the margin delay adjustment controller controls the margin time;
wherein the functional timing failure signal is generated by sensing a delay through the functional critical path relative to the trigger time for the next-level register using actual components of the functional critical path under current process, temperature, and voltage conditions with margin times adjusted for measured transistor wear.

10. The wear-sensing integrated circuit of claim 9 further comprising:
a VDD controller that receives the functional timing failure signal from the functional critical path timing sensor, the VDD controller causing a power-supply voltage to the plurality of registers and to the combinatorial logic to be increased when the functional timing failure signal is received, the VDD controller causing the power-supply voltage to be reduced when no functional timing failure signal is received for a period of time,
wherein the power-supply voltage is adjusted to compensate for functional timing failures detected through the functional critical paths.

11. The wear-sensing integrated circuit of claim 10 wherein each functional timing sensor comprises:
a margin delay buffer receiving the next-level input and driving a delayed input delayed by the margin time;
an early capture register that is clocked by the clock and generates a delayed output from the delayed input; and
a compare gate that compares the delayed output to the delayed input or to an output of the next-level register and activates the functional timing failure signal when the delayed output does not match.

12. A wear-compensating timing adjustor comprising:
an agi

Assignees

• Abreezio LLC
• Qualcomm Inc

Inventors

• Quinton Bradley
• McClements Trent
• Hughes Andrew
• Taneja Sanjiv

Classifications

• H03K2005/00019

  Variable delay · CPC title

• H03K5/13 Primary

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• G01R31/2858 Primary

  Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection · CPC title

• H03K3/0375

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title